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Message-ID: <20250825-deniable-quizzical-1d829756fff4@spud>
Date: Mon, 25 Aug 2025 17:25:55 +0100
From: Conor Dooley <conor@...nel.org>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: E Shattow <e@...eshell.de>, Rob Herring <robh@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, linux-riscv@...ts.infradead.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
Hal Feng <hal.feng@...rfivetech.com>,
Minda Chen <minda.chen@...rfivetech.com>
Subject: Re: [PATCH v3 1/3] dt-bindings: memory-controllers: add StarFive
JH7110 SoC DMC
On Sun, Aug 24, 2025 at 11:25:08AM +0200, Krzysztof Kozlowski wrote:
> On Sat, Aug 23, 2025 at 03:01:41AM -0700, E Shattow wrote:
> > Describe JH7110 SoC DDR external memory interface.
> >
> > Signed-off-by: E Shattow <e@...eshell.de>
> > ---
> > .../starfive,jh7110-dmc.yaml | 74 +++++++++++++++++++
> > 1 file changed, 74 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
>
> There is no memory controllers driver change, so I am fine if this goes
> via SoC/DTS tree. If you want me to pick it up, please ping on IRC.
That's cool, I will take it with the dts changes. Thanks.
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