linux-kernel - Re: [PATCH v2 01/11] arm64: dts: amlogic: Add cache information to the Amlogic GXBB and GXL SoC

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Message-ID: <CANAwSgQT7Y9_TKsYVignTOX1AWpcK6xEEU5+Dhy6Yd=ZG4qCjw@mail.gmail.com>
Date: Mon, 25 Aug 2025 18:27:44 +0530
From: Anand Moon <linux.amoon@...il.com>
To: Christian Hewitt <christian@...ittfamily.org.uk>
Cc: Neil Armstrong <neil.armstrong@...aro.org>, Kevin Hilman <khilman@...libre.com>, 
	Jerome Brunet <jbrunet@...libre.com>, 
	Martin Blumenstingl <martin.blumenstingl@...glemail.com>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	"moderated list:ARM/Amlogic Meson SoC support" <linux-arm-kernel@...ts.infradead.org>, 
	"open list:ARM/Amlogic Meson SoC support" <linux-amlogic@...ts.infradead.org>, 
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>, open list <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 01/11] arm64: dts: amlogic: Add cache information to
 the Amlogic GXBB and GXL SoC

Hi Christian,

On Mon, 25 Aug 2025 at 13:29, Christian Hewitt
<christian@...ittfamily.org.uk> wrote:
>
> > On 25 Aug 2025, at 10:51 am, Anand Moon <linux.amoon@...il.com> wrote:
> >
> > As per S905 and S905X datasheet add missing cache information to
> > the Amlogic GXBB and GXL SoC.
> >
> > - Each Cortex-A53 core has 32KB of L1 instruction cache available and
> > 32KB of L1 data cache available.
> > - Along with 512KB Unified L2 cache.
> >
> > Cache memory significantly reduces the time it takes for the CPU
> > to access data and instructions, leading to faster program execution
> > and overall system responsiveness.
>
> Hello Anand,
>
> I’m wondering if we are “enabling caching” in these patches (could be
> a significant gain, as per text) or we are “optimising caching” meaning
> the kernel currently assumes generic/safe defaults so having accurate
> descriptions in dt allows better efficiency (marginal gain)?
>
> Stats are also subjective to the workload used, but do you have any
> kind of before/after benchmarks? (for any of the SoCs in the patchset)
>

This is a fundamental feature of Arm64 CPUs that tracks active instructions
and data within cache-mapped memory pages.
Enabling it can significantly enhance overall system performance.

We can configure more l2 cache memory which is confribable as per the
Arm TRM document.
Arm Cortex - A53  - Configurable L2 cache size of 128KB, 256KB, 512KB,
1MB and 2MB.
Arm Cortex - A55  - Configurable L2 cache size of 64KB, 128KB, or 256KB
Arm Cortex - A73 -  Configurable L2 cache size of 256KB, 512KB, 1MB,
2MB, 4MB, or 8MB.

Here's an article that provides detailed insights into the cache feature.
[0] http://jake.dothome.co.kr/cache4/

I tested with a small benchmark to test factorial.

Before:>
alarm@...hl-librecm:~$ sudo perf stat -e cache-references,cache-misses ./test
Simulated Cache Miss Time (avg): 589 ns
Factorial(10) = 3628800

 Performance counter stats for './test':

           3017286      cache-references
             45414      cache-misses                     #    1.51% of
all cache refs

       0.054512394 seconds time elapsed

       0.004209000 seconds user
       0.041866000 seconds sys

After:>
 # sudo perf stat -e cache-references,cache-misses ./test
Simulated Cache Miss Time (avg): 426 ns
Factorial(10) = 3628800

 Performance counter stats for './test':

           2814633      cache-references
             27054      cache-misses                     #    0.96% of
all cache refs

       0.041041585 seconds time elapsed

       0.007976000 seconds user
       0.032009000 seconds sys

> Christian

Thanks
-Anand