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Message-Id: <DCEB1J2P3MZS.3IGXEYP0MAC5H@kernel.org>
Date: Thu, 28 Aug 2025 21:24:02 +0200
From: "Danilo Krummrich" <dakr@...nel.org>
To: "Miguel Ojeda" <ojeda@...nel.org>
Cc: "Alexandre Courbot" <acourbot@...dia.com>, "David Airlie"
<airlied@...il.com>, "Simona Vetter" <simona@...ll.ch>,
<nouveau@...ts.freedesktop.org>, <dri-devel@...ts.freedesktop.org>,
<rust-for-linux@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: gpu: nova-core: arm32 build errors
On Thu Aug 28, 2025 at 7:54 PM CEST, Danilo Krummrich wrote:
> On 8/28/25 6:02 PM, Miguel Ojeda wrote:
>> Similar to another one I sent, I hope it helps -- it may be useful to make it
>> build in 32-bit as a test for those kinds of platforms.
>
> Agreed.
Maybe I spoke too soon, it's actually pretty painful to keep 32-bit
compatibility, even though it would be nice for testing purposes.
I'll paste the diff to fix it below, I think that makes it obvious why I say
that.
Instead, we should really just depend on CONFIG_64BIT (which implies
ARCH_DMA_ADDR_T_64BIT).
--
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 50437c67c14a..e6a22834e317 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -466,7 +466,7 @@ fn dma_wr<F: FalconFirmware<Target = E>>(
.set_base((dma_start >> 8) as u32)
.write(bar, E::BASE);
regs::NV_PFALCON_FALCON_DMATRFBASE1::default()
- .set_base((dma_start >> 40) as u16)
+ .set_base((dma_start.checked_shr(40).unwrap_or(0)) as u16)
.write(bar, E::BASE);
let cmd = regs::NV_PFALCON_FALCON_DMATRFCMD::default()
diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/hal.rs
index 2f914948bb9a..710491ee445a 100644
--- a/drivers/gpu/nova-core/fb/hal.rs
+++ b/drivers/gpu/nova-core/fb/hal.rs
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
+use kernel::bindings::dma_addr_t as DmaAddress;
use kernel::prelude::*;
use crate::driver::Bar0;
@@ -11,12 +12,12 @@
pub(crate) trait FbHal {
/// Returns the address of the currently-registered sysmem flush page.
- fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64;
+ fn read_sysmem_flush_page(&self, bar: &Bar0) -> DmaAddress;
/// Register `addr` as the address of the sysmem flush page.
///
/// This might fail if the address is too large for the receiving register.
- fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result;
+ fn write_sysmem_flush_page(&self, bar: &Bar0, addr: DmaAddress) -> Result;
/// Returns `true` is display is supported.
fn supports_display(&self, bar: &Bar0) -> bool;
diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-core/fb/hal/ga100.rs
index 871c42bf033a..c4ae172b4ed4 100644
--- a/drivers/gpu/nova-core/fb/hal/ga100.rs
+++ b/drivers/gpu/nova-core/fb/hal/ga100.rs
@@ -2,6 +2,7 @@
struct Ga100;
+use kernel::bindings::dma_addr_t as DmaAddress;
use kernel::prelude::*;
use crate::driver::Bar0;
@@ -10,13 +11,22 @@
use super::tu102::FLUSH_SYSMEM_ADDR_SHIFT;
-pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> u64 {
- u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
+pub(super) fn read_sysmem_flush_page_ga100(bar: &Bar0) -> DmaAddress {
+ let addr = u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08())
+ << FLUSH_SYSMEM_ADDR_SHIFT
| u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::read(bar).adr_63_40())
- << FLUSH_SYSMEM_ADDR_SHIFT_HI
+ << FLUSH_SYSMEM_ADDR_SHIFT_HI;
+
+ addr.try_into().unwrap_or_else(|_| {
+ kernel::warn_on!(true);
+
+ 0
+ })
}
-pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: u64) {
+pub(super) fn write_sysmem_flush_page_ga100(bar: &Bar0, addr: DmaAddress) {
+ let addr = Into::<u64>::into(addr);
+
regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI::default()
.set_adr_63_40((addr >> FLUSH_SYSMEM_ADDR_SHIFT_HI) as u32)
.write(bar);
@@ -34,11 +44,11 @@ pub(super) fn display_enabled_ga100(bar: &Bar0) -> bool {
const FLUSH_SYSMEM_ADDR_SHIFT_HI: u32 = 40;
impl FbHal for Ga100 {
- fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 {
+ fn read_sysmem_flush_page(&self, bar: &Bar0) -> DmaAddress {
read_sysmem_flush_page_ga100(bar)
}
- fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {
+ fn write_sysmem_flush_page(&self, bar: &Bar0, addr: DmaAddress) -> Result {
write_sysmem_flush_page_ga100(bar, addr);
Ok(())
diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-core/fb/hal/ga102.rs
index a73b77e39715..271dfd522b3c 100644
--- a/drivers/gpu/nova-core/fb/hal/ga102.rs
+++ b/drivers/gpu/nova-core/fb/hal/ga102.rs
@@ -1,5 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
+use kernel::bindings::dma_addr_t as DmaAddress;
use kernel::prelude::*;
use crate::driver::Bar0;
@@ -13,11 +14,11 @@ fn vidmem_size_ga102(bar: &Bar0) -> u64 {
struct Ga102;
impl FbHal for Ga102 {
- fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 {
+ fn read_sysmem_flush_page(&self, bar: &Bar0) -> DmaAddress {
super::ga100::read_sysmem_flush_page_ga100(bar)
}
- fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {
+ fn write_sysmem_flush_page(&self, bar: &Bar0, addr: DmaAddress) -> Result {
super::ga100::write_sysmem_flush_page_ga100(bar, addr);
Ok(())
diff --git a/drivers/gpu/nova-core/fb/hal/tu102.rs b/drivers/gpu/nova-core/fb/hal/tu102.rs
index b022c781caf4..157342411596 100644
--- a/drivers/gpu/nova-core/fb/hal/tu102.rs
+++ b/drivers/gpu/nova-core/fb/hal/tu102.rs
@@ -3,17 +3,28 @@
use crate::driver::Bar0;
use crate::fb::hal::FbHal;
use crate::regs;
+
+use kernel::bindings::dma_addr_t as DmaAddress;
use kernel::prelude::*;
/// Shift applied to the sysmem address before it is written into `NV_PFB_NISO_FLUSH_SYSMEM_ADDR`,
/// to be used by HALs.
pub(super) const FLUSH_SYSMEM_ADDR_SHIFT: u32 = 8;
-pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> u64 {
- u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08()) << FLUSH_SYSMEM_ADDR_SHIFT
+pub(super) fn read_sysmem_flush_page_gm107(bar: &Bar0) -> DmaAddress {
+ let addr = u64::from(regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::read(bar).adr_39_08())
+ << FLUSH_SYSMEM_ADDR_SHIFT;
+
+ addr.try_into().unwrap_or_else(|_| {
+ kernel::warn_on!(true);
+
+ 0
+ })
}
-pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: u64) -> Result {
+pub(super) fn write_sysmem_flush_page_gm107(bar: &Bar0, addr: DmaAddress) -> Result {
+ let addr = Into::<u64>::into(addr);
+
// Check that the address doesn't overflow the receiving 32-bit register.
if addr >> (u32::BITS + FLUSH_SYSMEM_ADDR_SHIFT) == 0 {
regs::NV_PFB_NISO_FLUSH_SYSMEM_ADDR::default()
@@ -37,11 +48,11 @@ pub(super) fn vidmem_size_gp102(bar: &Bar0) -> u64 {
struct Tu102;
impl FbHal for Tu102 {
- fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 {
+ fn read_sysmem_flush_page(&self, bar: &Bar0) -> DmaAddress {
read_sysmem_flush_page_gm107(bar)
}
- fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result {
+ fn write_sysmem_flush_page(&self, bar: &Bar0, addr: DmaAddress) -> Result {
write_sysmem_flush_page_gm107(bar, addr)
}
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