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Message-ID: <08d79767-4b9b-41c3-8d51-5ff879eacb31@oracle.com>
Date: Thu, 28 Aug 2025 16:48:48 +0530
From: ALOK TIWARI <alok.a.tiwari@...cle.com>
To: Chen Wang <unicornxw@...il.com>, kwilczynski@...nel.org,
u.kleine-koenig@...libre.com, aou@...s.berkeley.edu, alex@...ti.fr,
arnd@...db.de, bwawrzyn@...co.com, bhelgaas@...gle.com,
unicorn_wang@...look.com, conor+dt@...nel.org, 18255117159@....com,
inochiama@...il.com, kishon@...nel.org, krzk+dt@...nel.org,
lpieralisi@...nel.org, mani@...nel.org, palmer@...belt.com,
paul.walmsley@...ive.com, robh@...nel.org, s-vadapalli@...com,
tglx@...utronix.de, thomas.richard@...tlin.com,
sycamoremoon376@...il.com, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
linux-riscv@...ts.infradead.org, sophgo@...ts.linux.dev,
rabenda.cn@...il.com, chao.wei@...hgo.com, xiaoguang.xing@...hgo.com,
fengchun.li@...hgo.com
Subject: Re: [PATCH 3/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver
On 8/28/2025 7:47 AM, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@...look.com>
>
> Add support for PCIe controller in SG2042 SoC. The controller
> uses the Cadence PCIe core programmed by pcie-cadence*.c. The
> PCIe controller will work in host mode only.
>
> Signed-off-by: Chen Wang <unicorn_wang@...look.com>
> ---
> drivers/pci/controller/cadence/Kconfig | 12 ++
> drivers/pci/controller/cadence/Makefile | 1 +
> drivers/pci/controller/cadence/pcie-sg2042.c | 134 +++++++++++++++++++
> 3 files changed, 147 insertions(+)
> create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c
>
> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig
> index 666e16b6367f..b1f1941d5208 100644
> --- a/drivers/pci/controller/cadence/Kconfig
> +++ b/drivers/pci/controller/cadence/Kconfig
> @@ -42,6 +42,17 @@ config PCIE_CADENCE_PLAT_EP
> endpoint mode. This PCIe controller may be embedded into many
> different vendors SoCs.
>
> +config PCIE_SG2042
> + bool "Sophgo SG2042 PCIe controller (host mode)"
> + depends on ARCH_SOPHGO || COMPILE_TEST
> + depends on OF
> + depends on PCI_MSI
> + select PCIE_CADENCE_HOST
> + help
> + Say Y here if you want to support the Sophgo SG2042 PCIe platform
> + controller in host mode. Sophgo SG2042 PCIe controller uses Cadence
> + PCIe core.
> +
> config PCI_J721E
> tristate
> select PCIE_CADENCE_HOST if PCI_J721E_HOST != n
> @@ -67,4 +78,5 @@ config PCI_J721E_EP
> Say Y here if you want to support the TI J721E PCIe platform
> controller in endpoint mode. TI J721E PCIe controller uses Cadence PCIe
> core.
> +
> endmenu
> diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controller/cadence/Makefile
> index 9bac5fb2f13d..4df4456d9539 100644
> --- a/drivers/pci/controller/cadence/Makefile
> +++ b/drivers/pci/controller/cadence/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o
> obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o
> obj-$(CONFIG_PCIE_CADENCE_PLAT) += pcie-cadence-plat.o
> obj-$(CONFIG_PCI_J721E) += pci-j721e.o
> +obj-$(CONFIG_PCIE_SG2042) += pcie-sg2042.o
> diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c
> new file mode 100644
> index 000000000000..fe434dc2967e
> --- /dev/null
> +++ b/drivers/pci/controller/cadence/pcie-sg2042.c
> @@ -0,0 +1,134 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC
> + *
> + * Copyright (C) 2025 Sophgo Technology Inc.
> + * Copyright (C) 2025 Chen Wang <unicorn_wang@...look.com>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/of.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "pcie-cadence.h"
> +
> +/*
> + * SG2042 only support 4-byte aligned access, so for the rootbus (i.e. to read
support -> supports
> + * the Root Port itself, read32 is required. For non-rootbus (i.e. to read
> + * the PCIe peripheral registers, supports 1/2/4 byte aligned access, so
> + * directly using read should be fine.
> + *
> + * The same is true for write.
[clip]
> +static int sg2042_pcie_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct pci_host_bridge *bridge;
> + struct cdns_pcie *pcie;
> + struct cdns_pcie_rc *rc;
> + int ret;
> +
> + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> + if (!pcie)
> + return -ENOMEM;
> +
> + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc));
> + if (!bridge) {
> + dev_err(dev, "Failed to alloc host bridge!\n");
> + return -ENOMEM;
> + }
> +
> + bridge->ops = &sg2042_pcie_host_ops;
> +
> + rc = pci_host_bridge_priv(bridge);
> + pcie = &rc->pcie;
First, pcie is allocated and then reassigned to &rc->pcie,
which makes the initial allocation effectively leaked and unnecessary.
> + pcie->dev = dev;
> +
> + platform_set_drvdata(pdev, pcie);
> +
> + pm_runtime_enable(dev);
> +
> + ret = pm_runtime_get_sync(dev);
> + if (ret < 0) {
> + dev_err(dev, "pm_runtime_get_sync failed\n");
> + goto err_get_sync;
> + }
> +
> + ret = cdns_pcie_init_phy(dev, pcie);
> + if (ret) {
> + dev_err(dev, "Failed to init phy!\n");
> + goto err_get_sync;
> + }
> +
> + ret = cdns_pcie_host_setup(rc);
> + if (ret < 0) {
> + dev_err(dev, "Failed to setup host!\n");
> + goto err_host_setup;
> + }
> +
> + return 0;
> +
> +err_host_setup:
> + cdns_pcie_disable_phy(pcie);
> +
> +err_get_sync:
> + pm_runtime_put(dev);
> + pm_runtime_disable(dev);
> +
> + return ret;
> +}
Thanks,
Alok
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