linux-kernel - Re: [PATCH 5/8] clk: sophgo: sg2042-clkgen: convert from round_rate() to determine

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Message-ID:
 <MAUPR01MB11072DB589F1E6B1E18D329A6FE3AA@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM>
Date: Fri, 29 Aug 2025 11:10:15 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Brian Masney <bmasney@...hat.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Vladimir Zapolskiy <vz@...ia.com>,
 Piotr Wojtaszczyk <piotr.wojtaszczyk@...esys.com>,
 Inochi Amaoto <inochiama@...il.com>, Michal Simek <michal.simek@....com>,
 Bjorn Andersson <andersson@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
 Andrea della Porta <andrea.porta@...e.com>,
 Maxime Ripard <mripard@...nel.org>
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
 linux-kernel@...r.kernel.org, sophgo@...ts.linux.dev,
 linux-arm-msm@...r.kernel.org, linux-rockchip@...ts.infradead.org
Subject: Re: [PATCH 5/8] clk: sophgo: sg2042-clkgen: convert from round_rate()
 to determine_rate()


On 8/29/2025 8:38 AM, Brian Masney wrote:
> The round_rate() clk ops is deprecated, so migrate this driver from
> round_rate() to determine_rate() using the Coccinelle semantic patch
> on the cover letter of this series.
>
> Reviewed-by: Chen Wang <unicorn_wang@...look.com>
> Signed-off-by: Brian Masney <bmasney@...hat.com>

Tested-by: Chen Wang <unicorn_wang@...look.com> # Pioneerbox

Thanks,

Chen

> ---
>   drivers/clk/sophgo/clk-sg2042-clkgen.c | 17 +++++++++--------
>   1 file changed, 9 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/clk/sophgo/clk-sg2042-clkgen.c b/drivers/clk/sophgo/clk-sg2042-clkgen.c
> index 9e61288d34f3757315702c355f2669577b29676f..683661b71787c9e5428b168502f6fbb30ea9f7da 100644
> --- a/drivers/clk/sophgo/clk-sg2042-clkgen.c
> +++ b/drivers/clk/sophgo/clk-sg2042-clkgen.c
> @@ -176,9 +176,8 @@ static unsigned long sg2042_clk_divider_recalc_rate(struct clk_hw *hw,
>   	return ret_rate;
>   }
>   
> -static long sg2042_clk_divider_round_rate(struct clk_hw *hw,
> -					  unsigned long rate,
> -					  unsigned long *prate)
> +static int sg2042_clk_divider_determine_rate(struct clk_hw *hw,
> +					     struct clk_rate_request *req)
>   {
>   	struct sg2042_divider_clock *divider = to_sg2042_clk_divider(hw);
>   	unsigned long ret_rate;
> @@ -192,15 +191,17 @@ static long sg2042_clk_divider_round_rate(struct clk_hw *hw,
>   			bestdiv = readl(divider->reg) >> divider->shift;
>   			bestdiv &= clk_div_mask(divider->width);
>   		}
> -		ret_rate = DIV_ROUND_UP_ULL((u64)*prate, bestdiv);
> +		ret_rate = DIV_ROUND_UP_ULL((u64)req->best_parent_rate, bestdiv);
>   	} else {
> -		ret_rate = divider_round_rate(hw, rate, prate, NULL,
> +		ret_rate = divider_round_rate(hw, req->rate, &req->best_parent_rate, NULL,
>   					      divider->width, divider->div_flags);
>   	}
>   
>   	pr_debug("--> %s: divider_round_rate: val = %ld\n",
>   		 clk_hw_get_name(hw), ret_rate);
> -	return ret_rate;
> +	req->rate = ret_rate;
> +
> +	return 0;
>   }
>   
>   static int sg2042_clk_divider_set_rate(struct clk_hw *hw,
> @@ -258,13 +259,13 @@ static int sg2042_clk_divider_set_rate(struct clk_hw *hw,
>   
>   static const struct clk_ops sg2042_clk_divider_ops = {
>   	.recalc_rate = sg2042_clk_divider_recalc_rate,
> -	.round_rate = sg2042_clk_divider_round_rate,
> +	.determine_rate = sg2042_clk_divider_determine_rate,
>   	.set_rate = sg2042_clk_divider_set_rate,
>   };
>   
>   static const struct clk_ops sg2042_clk_divider_ro_ops = {
>   	.recalc_rate = sg2042_clk_divider_recalc_rate,
> -	.round_rate = sg2042_clk_divider_round_rate,
> +	.determine_rate = sg2042_clk_divider_determine_rate,
>   };
>   
>   /*
>