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Message-Id: <20250830-msm8953-spi-fix-v1-3-89950eaf10fe@mainlining.org>
Date: Sat, 30 Aug 2025 23:13:21 +0200
From: Barnabás Czémán <barnabas.czeman@...nlining.org>
To: Bjorn Andersson <andersson@...nel.org>, 
 Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Gianluca Boiano <morf3089@...il.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, 
 Barnabás Czémán <barnabas.czeman@...nlining.org>
Subject: [PATCH 3/3] arm64: dts: qcom: msm8953: add spi_7

Add spi_7 can be found in MSM8953 devices.

Signed-off-by: Barnabás Czémán <barnabas.czeman@...nlining.org>
---
 arch/arm64/boot/dts/qcom/msm8953.dtsi | 52 +++++++++++++++++++++++++++++++++++
 1 file changed, 52 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 1b3e68aed9450f61d14fe6c16a4dd513c815c6da..76317c5783496675a549815bbed71fd214590dd1 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -870,6 +870,38 @@ spi-pins {
 				};
 			};
 
+			spi_7_default: spi-7-default-state {
+				cs-pins {
+					pins = "gpio136";
+					function = "blsp_spi7";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio135", "gpio137", "gpio138";
+					function = "blsp_spi7";
+					drive-strength = <12>;
+					bias-disable;
+				};
+			};
+
+			spi_7_sleep: spi-7-sleep-state {
+				cs-pins {
+					pins = "gpio136";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-disable;
+				};
+
+				spi-pins {
+					pins = "gpio135", "gpio137", "gpio138";
+					function = "gpio";
+					drive-strength = <2>;
+					bias-pull-down;
+				};
+			};
+
 			uart_5_default: uart-5-default-state {
 				pins = "gpio16", "gpio17", "gpio18", "gpio19";
 				function = "blsp_uart5";
@@ -1880,6 +1912,26 @@ i2c_7: i2c@...7000 {
 			status = "disabled";
 		};
 
+		spi_7: spi@...7000 {
+			compatible = "qcom,spi-qup-v2.2.1";
+			reg = <0x07af7000 0x600>;
+			interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "core", "iface";
+			clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>,
+				 <&gcc GCC_BLSP2_AHB_CLK>;
+			dmas = <&blsp2_dma 8>, <&blsp2_dma 9>;
+			dma-names = "tx", "rx";
+
+			pinctrl-names = "default", "sleep";
+			pinctrl-0 = <&spi_7_default>;
+			pinctrl-1 = <&spi_7_sleep>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
 		i2c_8: i2c@...8000 {
 			compatible = "qcom,i2c-qup-v2.2.1";
 			reg = <0x07af8000 0x600>;

-- 
2.51.0


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