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Message-ID: <9e56d3e2-b9c4-41ee-aab2-220733fbd658@kernel.og>
Date: Sat, 30 Aug 2025 20:40:45 -0500
From: Dinh Nguyen <dinguyen@...nel.og>
To: yankei.fong@...era.com, Dinh Nguyen <dinguyen@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>, open list <linux-kernel@...r.kernel.org>,
Matthew Gerlach <matthew.gerlach@...era.com>
Subject: Re: [PATCH 1/4] arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
On 6/24/25 01:52, yankei.fong@...era.com wrote:
> From: "Fong, Yan Kei" <yan.kei.fong@...era.com>
>
> Add spi-tx-bus-width and spi-rx-bus-width properties with
> value 4 to the n5x device tree.
> This update configures the SPI controller to use a 4-bit
> bus width for both transmission and reception,
> potentially improving SPI throughput and
> matching the hardware capabilities more closely.
Please use 80 columns for your commit message! Like this:
Add spi-tx-bus-width and spi-rx-bus-width properties with value 4 to the
n5x device tree. This update configures the SPI controller to use a
4-bit bus width for both transmission and reception, potentially
improving SPI throughput and matching the hardware capabilities more
closely.
Doesn't the above make it much easier to read? Please do this fall your
patches from now on!
Dinh
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