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Message-ID:
 <BL1PR03MB6088383692B602E169494FB5AB49A@BL1PR03MB6088.namprd03.prod.outlook.com>
Date: Wed, 9 Jul 2025 07:00:28 +0000
From: "Fong, Yan Kei" <yan.kei.fong@...era.com>
To: Dinh Nguyen <dinguyen@...nel.org>, Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
	<devicetree@...r.kernel.org>, open list <linux-kernel@...r.kernel.org>,
	"Gerlach, Matthew" <matthew.gerlach@...era.com>
Subject: RE: [PATCH 0/4] Add 4-bit SPI bus width on target devices

> On 6/24/25 01:52, yankei.fong@...era.com wrote:
> > From: "Fong, Yan Kei" <yan.kei.fong@...era.com>
> >
> > Add SPI bus width properties to correctly describe the hardware on the
> following devices:
> >   - Stratix10
> >   - Agilex
> >   - Agilex5
> >   - N5X
> >
> > Fong, Yan Kei (4):
> >    arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
> >    arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
> >    arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
> >    arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
> >
> >   arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 2 ++
> >   arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts    | 2 ++
> >   arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts     | 2 ++
> >   arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts        | 2 ++
> >   4 files changed, 8 insertions(+)
> >
> 
> This is for the QSPI driver right? I don't even see the driver using this property.
> So how would this help?

Yes, it's for QSPI driver. The bindings (spi-tx-bus-width and spi-rx-bus-width) are defined in Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml. They are read in of_spi_parse_dt() which is ultimately called from spi_register_controller().

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