linux-kernel - Re: [PATCH v4 4/5] arm64: initialise SCTLR2_EL1 at cpu_soft

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <aLXm5/R+mrsnT7tn@e129823.arm.com>
Date: Mon, 1 Sep 2025 19:33:11 +0100
From: Yeoreum Yun <yeoreum.yun@....com>
To: Dave Martin <Dave.Martin@....com>
Cc: catalin.marinas@....com, will@...nel.org, broonie@...nel.org,
	oliver.upton@...ux.dev, anshuman.khandual@....com, robh@...nel.org,
	james.morse@....com, mark.rutland@....com, joey.gouly@....com,
	ahmed.genidi@....com, kevin.brodsky@....com,
	scott@...amperecomputing.com, mbenes@...e.cz,
	james.clark@...aro.org, frederic@...nel.org, rafael@...nel.org,
	pavel@...nel.org, ryan.roberts@....com, suzuki.poulose@....com,
	maz@...nel.org, linux-arm-kernel@...ts.infradead.org,
	linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
	kvmarm@...ts.linux.dev
Subject: Re: [PATCH v4 4/5] arm64: initialise SCTLR2_EL1 at cpu_soft_restart()

Hi Dave,

> > Explicitly initialize the SCTLR2_ELx register before launching
> > a new kernel via kexec() to avoid leaving SCTLR2_ELx with an
> > arbitrary value when the new kernel runs.
> >
> > Signed-off-by: Yeoreum Yun <yeoreum.yun@....com>
> > ---
> >  arch/arm64/kernel/cpu-reset.S      | 4 ++++
> >  arch/arm64/kvm/hyp/nvhe/hyp-init.S | 3 +++
> >  2 files changed, 7 insertions(+)
> >
> > diff --git a/arch/arm64/kernel/cpu-reset.S b/arch/arm64/kernel/cpu-reset.S
> > index c87445dde674..c8888891dc8d 100644
> > --- a/arch/arm64/kernel/cpu-reset.S
> > +++ b/arch/arm64/kernel/cpu-reset.S
> > @@ -37,6 +37,10 @@ SYM_TYPED_FUNC_START(cpu_soft_restart)
> >  	 * regime if HCR_EL2.E2H == 1
> >  	 */
> >  	msr	sctlr_el1, x12
> > +
> > +	mov_q	x12, INIT_SCTLR2_EL1
> > +	set_sctlr2_elx	1, x12, x8
> > +
>
> Nit: does it matter whether we reset SCTLR2 before SCTLR?
>
> I can't find a convincing architectural reason why they need to be
> reset in a particular order, but it looks a bit strange that the
> cpu_soft_restart and __kvm_handle_stub_hvc versions of this reset the
> registers in the opposite order...

TBH, I couldn't find the reason why SCTLR2_ELx should be initilized
before SCTLR_EL1. I don't think current bits on SCTLR2_ELx doesn't have
any effects from SCTLR_EL1 (MMU bit and etc) and vice versa.

But as other code, as you mention, it would be better to reorder this
initialization.

Thanks!

[...]

--
Sincerely,
Yeoreum Yun