linux-kernel - Re: [PATCH v1] clk: renesas: r8a779g0: Add ZG clocks

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Message-ID: <CAMuHMdXTqhjqr2E7XtyamtzGf=t1vSdz+0urRY+=BVYgF_qdMg@mail.gmail.com>
Date: Mon, 1 Sep 2025 12:09:01 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Anh Nguyen <anh.nguyen.pv@...esas.com>
Cc: "mturquette@...libre.com" <mturquette@...libre.com>, "sboyd@...nel.org" <sboyd@...nel.org>, 
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>, 
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>, 
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, 
	Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>, Duy Dang <duy.dang.yw@...esas.com>, 
	Duy Nguyen <duy.nguyen.rh@...esas.com>
Subject: Re: [PATCH v1] clk: renesas: r8a779g0: Add ZG clocks

Hi Anh,

On Mon, 25 Aug 2025 at 06:33, Anh Nguyen <anh.nguyen.pv@...esas.com> wrote:
> From decde7c45060327ecb24df8218cd58b9ffd3c45d Mon Sep 17 00:00:00 2001
> From: Anh Nguyen <anh.nguyen.pv@...esas.com>
> Date: Thu, 21 Aug 2025 09:54:00 +0700
> Subject: [PATCH 1/2] clk: renesas: r8a779g0: Add ZG clocks
>
> Add ZG related clocks for GSX
>
> Signed-off-by: Anh Nguyen <anh.nguyen.pv@...esas.com>
> Reviewed-by: Kuninori Morimoto <kuninori.morimoto.gx@...esas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779g0-cpg-mssr.c
> @@ -151,6 +151,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
>         DEF_FIXED("dsiref",     R8A779G0_CLK_DSIREF,    CLK_PLL5_DIV4,  48, 1),
>         DEF_DIV6P1("dsiext",    R8A779G0_CLK_DSIEXT,    CLK_PLL5_DIV4,  CPG_DSIEXTCKCR),
>
> +       DEF_FIXED("zg",         R8A779G0_CLK_ZG,        CLK_PLL4_DIV2,  2, 1),

According to the documentation, this is not a fixed clock, but uses
a programmable divider in the FRQCRB register.

>         DEF_GEN4_SDH("sd0h",    R8A779G0_CLK_SD0H,      CLK_SDSRC,         CPG_SD0CKCR),
>         DEF_GEN4_SD("sd0",      R8A779G0_CLK_SD0,       R8A779G0_CLK_SD0H, CPG_SD0CKCR),
>         DEF_DIV6P1("mso",       R8A779G0_CLK_MSO,       CLK_PLL5_DIV4,  CPG_MSOCKCR),
> @@ -163,6 +164,7 @@ static const struct cpg_core_clk r8a779g0_core_clks[] __initconst = {
>  };
>
>  static const struct mssr_mod_clk r8a779g0_mod_clks[] __initconst = {
> +       DEF_MOD("rgx",            0,    R8A779G0_CLK_ZG),

Perhaps "3dge", to match the documentation?

>         DEF_MOD("isp0",          16,    R8A779G0_CLK_S0D2_VIO),
>         DEF_MOD("isp1",          17,    R8A779G0_CLK_S0D2_VIO),
>         DEF_MOD("avb0",         211,    R8A779G0_CLK_S0D4_HSC),

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds