linux-kernel - Re: [PATCH v4 11/19] drm/mediatek: Rename OVL format naming

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Message-ID: <06e8b1c561ff54f1946cc3727e8f95420c5a337a.camel@mediatek.com>
Date: Mon, 1 Sep 2025 02:45:21 +0000
From: CK Hu (胡俊光) <ck.hu@...iatek.com>
To: "robh@...nel.org" <robh@...nel.org>, "krzk+dt@...nel.org"
	<krzk+dt@...nel.org>, Paul-pl Chen (陳柏霖)
	<Paul-pl.Chen@...iatek.com>, "conor+dt@...nel.org" <conor+dt@...nel.org>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	"chunkuang.hu@...nel.org" <chunkuang.hu@...nel.org>
CC: Sunny Shen (沈姍姍) <Sunny.Shen@...iatek.com>,
	Sirius Wang (王皓昱) <Sirius.Wang@...iatek.com>,
	Nancy Lin (林欣螢) <Nancy.Lin@...iatek.com>,
	Xiandong Wang (王先冬)
	<Xiandong.Wang@...iatek.com>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "dri-devel@...ts.freedesktop.org"
	<dri-devel@...ts.freedesktop.org>, Project_Global_Chrome_Upstream_Group
	<Project_Global_Chrome_Upstream_Group@...iatek.com>,
	"linux-mediatek@...ts.infradead.org" <linux-mediatek@...ts.infradead.org>,
	Jason-JH Lin (林睿祥) <Jason-JH.Lin@...iatek.com>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"fshao@...omium.org" <fshao@...omium.org>, "p.zabel@...gutronix.de"
	<p.zabel@...gutronix.de>, Singo Chang (張興國)
	<Singo.Chang@...iatek.com>, "linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "matthias.bgg@...il.com"
	<matthias.bgg@...il.com>, "treapking@...omium.org" <treapking@...omium.org>
Subject: Re: [PATCH v4 11/19] drm/mediatek: Rename OVL format naming

On Thu, 2025-08-28 at 16:07 +0800, Paul Chen wrote:
> From: Paul-pl Chen <paul-pl.chen@...iatek.com>
> 
> Rename the OVL format naming

This patch looks good to me, but commit message is not good to me.
You should include three important things in one patch.

WHAT does this patch do: describe what does this patch do in title.
WHY this patch: describe why need this patch. I need a reason to apply this patch.
HOW to do: commit body would show how to do. HOW should be related to WHAT.

You does not show WHY need this patch.
Describe the reason why I need this patch.

Regards,
CK

> 
> Signed-off-by: Paul-pl Chen <paul-pl.chen@...iatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 32 ++++++++++++-------------
>  1 file changed, 16 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> index e0236353d499..d4f096d37abc 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
> @@ -101,7 +101,7 @@ static inline bool is_10bit_rgb(u32 fmt)
>  	return false;
>  }
>  
> -static const u32 mt8173_formats[] = {
> +static const u32 mt8173_ovl_formats[] = {
>  	DRM_FORMAT_XRGB8888,
>  	DRM_FORMAT_ARGB8888,
>  	DRM_FORMAT_BGRX8888,
> @@ -115,7 +115,7 @@ static const u32 mt8173_formats[] = {
>  	DRM_FORMAT_YUYV,
>  };
>  
> -static const u32 mt8195_formats[] = {
> +static const u32 mt8195_ovl_formats[] = {
>  	DRM_FORMAT_XRGB8888,
>  	DRM_FORMAT_ARGB8888,
>  	DRM_FORMAT_XRGB2101010,
> @@ -667,8 +667,8 @@ static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = {
>  	.gmc_bits = 8,
>  	.layer_nr = 4,
>  	.fmt_rgb565_is_0 = false,
> -	.formats = mt8173_formats,
> -	.num_formats = ARRAY_SIZE(mt8173_formats),
> +	.formats = mt8173_ovl_formats,
> +	.num_formats = ARRAY_SIZE(mt8173_ovl_formats),
>  };
>  
>  static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
> @@ -676,8 +676,8 @@ static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = {
>  	.gmc_bits = 8,
>  	.layer_nr = 4,
>  	.fmt_rgb565_is_0 = true,
> -	.formats = mt8173_formats,
> -	.num_formats = ARRAY_SIZE(mt8173_formats),
> +	.formats = mt8173_ovl_formats,
> +	.num_formats = ARRAY_SIZE(mt8173_ovl_formats),
>  };
>  
>  static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
> @@ -685,8 +685,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_driver_data = {
>  	.gmc_bits = 10,
>  	.layer_nr = 4,
>  	.fmt_rgb565_is_0 = true,
> -	.formats = mt8173_formats,
> -	.num_formats = ARRAY_SIZE(mt8173_formats),
> +	.formats = mt8173_ovl_formats,
> +	.num_formats = ARRAY_SIZE(mt8173_ovl_formats),
>  };
>  
>  static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
> @@ -694,8 +694,8 @@ static const struct mtk_disp_ovl_data mt8183_ovl_2l_driver_data = {
>  	.gmc_bits = 10,
>  	.layer_nr = 2,
>  	.fmt_rgb565_is_0 = true,
> -	.formats = mt8173_formats,
> -	.num_formats = ARRAY_SIZE(mt8173_formats),
> +	.formats = mt8173_ovl_formats,
> +	.num_formats = ARRAY_SIZE(mt8173_ovl_formats),
>  };
>  
>  static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
> @@ -707,8 +707,8 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
>  	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
>  		       BIT(DRM_MODE_BLEND_COVERAGE) |
>  		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
> -	.formats = mt8173_formats,
> -	.num_formats = ARRAY_SIZE(mt8173_formats),
> +	.formats = mt8173_ovl_formats,
> +	.num_formats = ARRAY_SIZE(mt8173_ovl_formats),
>  };
>  
>  static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
> @@ -720,8 +720,8 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
>  	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
>  		       BIT(DRM_MODE_BLEND_COVERAGE) |
>  		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
> -	.formats = mt8173_formats,
> -	.num_formats = ARRAY_SIZE(mt8173_formats),
> +	.formats = mt8173_ovl_formats,
> +	.num_formats = ARRAY_SIZE(mt8173_ovl_formats),
>  };
>  
>  static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
> @@ -734,8 +734,8 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
>  	.blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
>  		       BIT(DRM_MODE_BLEND_COVERAGE) |
>  		       BIT(DRM_MODE_BLEND_PIXEL_NONE),
> -	.formats = mt8195_formats,
> -	.num_formats = ARRAY_SIZE(mt8195_formats),
> +	.formats = mt8195_ovl_formats,
> +	.num_formats = ARRAY_SIZE(mt8195_ovl_formats),
>  	.supports_clrfmt_ext = true,
>  };
>