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Message-ID: <87y0qx0zqu.ffs@tglx>
Date: Tue, 02 Sep 2025 15:07:21 +0200
From: Thomas Gleixner <tglx@...utronix.de>
To: Ryan Chen <ryan_chen@...eedtech.com>, ryan_chen
<ryan_chen@...eedtech.com>, Eddie James <eajames@...ux.ibm.com>, Rob
Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor
Dooley <conor+dt@...nel.org>, Joel Stanley <joel@....id.au>, Andrew
Jeffery <andrew@...econstruct.com.au>, Lee Jones <lee@...nel.org>,
linux-aspeed@...ts.ozlabs.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 4/4] irqchip/aspeed-scu-ic: Add support AST2700 SCU
interrupt controllers
On Sun, Aug 31 2025 at 10:14, Ryan Chen wrote:
> The AST2700 continues the multi-instance SCU interrupt controller model
> introduced in the AST2600, with four independent interrupt domains
> (scu-ic0 to 3).
>
> Unlike earlier generations that combine interrupt enable and status bits
> into a single register, the AST2700 separates these into distinct IER and
> ISR registers. Support for this layout is implemented by using register
> offsets and separate chained IRQ handlers.
>
> The variant table is extended to cover AST2700 IC instances, enabling
> shared initialization logic while preserving support for previous SoCs.
>
> Signed-off-by: Ryan Chen <ryan_chen@...eedtech.com>
> ---
> drivers/irqchip/irq-aspeed-scu-ic.c | 123 +++++++++++++++++++++-------
> 1 file changed, 95 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/irqchip/irq-aspeed-scu-ic.c b/drivers/irqchip/irq-aspeed-scu-ic.c
> index cbfc35919281..ffdd9b4e44c1 100644
> --- a/drivers/irqchip/irq-aspeed-scu-ic.c
> +++ b/drivers/irqchip/irq-aspeed-scu-ic.c
> @@ -17,12 +17,16 @@
>
> #define ASPEED_SCU_IC_STATUS GENMASK(28, 16)
> #define ASPEED_SCU_IC_STATUS_SHIFT 16
> +#define AST2700_SCU_IC_STATUS GENMASK(15, 0)
>
> struct aspeed_scu_ic_variant {
> const char *compatible;
> unsigned long irq_enable;
> unsigned long irq_shift;
> unsigned int num_irqs;
> + bool split_ier_isr;
How does that end up aligned?
> + unsigned long ier;
> + unsigned long isr;
> };
>
> #define SCU_VARIANT(_compat, _shift, _enable, _num) { \
> @@ -30,13 +34,20 @@ struct aspeed_scu_ic_variant {
> .irq_shift = _shift, \
> .irq_enable = _enable, \
> .num_irqs = _num, \
> + .split_ier_isr = _split, \
Ditto.
> + .ier = _ier, \
> + .isr = _isr, \
But what's worse is that '_split, _ier and _isr' come out of thin air as
SCU_VARIANT does not have corresponding arguments. So how is that
supposed to work?
> }
>
> struct aspeed_scu_ic {
> @@ -45,9 +56,12 @@ struct aspeed_scu_ic {
> unsigned int num_irqs;
> void __iomem *base;
> struct irq_domain *irq_domain;
> + bool split_ier_isr;
Sigh...
> + unsigned long ier;
> + unsigned long isr;
> };
>
> -static void aspeed_scu_ic_irq_handler(struct irq_desc *desc)
> +static void aspeed_scu_ic_irq_handler_combined(struct irq_desc *desc)
> {
> struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc);
> struct irq_chip *chip = irq_desc_get_chip(desc);
> @@ -84,33 +98,69 @@ static void aspeed_scu_ic_irq_handler(struct irq_desc *desc)
> chained_irq_exit(chip, desc);
> }
>
> +static void aspeed_scu_ic_irq_handler_split(struct irq_desc *desc)
> +{
...
> static void aspeed_scu_ic_irq_mask(struct irq_data *data)
> {
> struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);
> - unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift) |
> - (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
>
> - /*
> - * Status bits are cleared by writing 1. In order to prevent the mask
> - * operation from clearing the status bits, they should be under the
> - * mask and written with 0.
> - */
> - writel(readl(scu_ic->base) & ~mask, scu_ic->base);
> + if (scu_ic->split_ier_isr) {
> + writel(readl(scu_ic->base) & ~BIT(data->hwirq + scu_ic->irq_shift),
> + scu_ic->base + scu_ic->ier);
> + } else {
> + unsigned int mask = BIT(data->hwirq + scu_ic->irq_shift) |
> + (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
> +
> + /*
> + * Status bits are cleared by writing 1. In order to prevent the mask
> + * operation from clearing the status bits, they should be under the
> + * mask and written with 0.
> + */
> + writel(readl(scu_ic->base) & ~mask, scu_ic->base);
> + }
So you have two different handlers. Why can't you provide two different
mask/unmask/ functions along with a seperate irq chip instead of
cluttering the code with conditionals. Thes two variants share no code
at all.
> - irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler,
> - scu_ic);
> + if (scu_ic->split_ier_isr)
> + irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler_split,
> + scu_ic);
> + else
> + irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler_combined,
> + scu_ic);
>
Please get rid of the line break. You have 100 characters....
Thanks,
tglx
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