linux-kernel - Re: [PATCH v2 2/2] clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks

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Message-ID: <CAMuHMdWARu=9__pqcHXUq92LYuxAQPZNJ6Fn_b7Z6x78i4twDw@mail.gmail.com>
Date: Tue, 2 Sep 2025 15:01:13 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Prabhakar <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, linux-renesas-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
	devicetree@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 2/2] clk: renesas: r9a09g077: Add Ethernet Subsystem
 core and module clocks

Hi Prabhakar,

On Mon, 1 Sept 2025 at 20:30, Prabhakar <prabhakar.csengg@...il.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>
> Add module and core clocks used by Ethernet Subsystem (Ethernet_SS),
> Ethernet MAC (GMAC), Ethernet Switch (ETHSW).
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a09g077-cpg.c
> +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> @@ -72,7 +72,7 @@ enum rzt2h_clk_types {
>
>  enum clk_ids {
>         /* Core Clock Outputs exported to DT */
> -       LAST_DT_CORE_CLK = R9A09G077_USB_CLK,
> +       LAST_DT_CORE_CLK = R9A09G077_GMAC2_PCLKAH,
>
>         /* External Input Clocks */
>         CLK_EXTAL,
> @@ -166,11 +166,21 @@ static const struct cpg_core_clk r9a09g077_core_clks[] __initconst = {
>         DEF_DIV("CA55S", R9A09G077_CLK_CA55S, CLK_SEL_CLK_PLL0, DIVCA55S,
>                 dtable_1_2),
>         DEF_FIXED("PCLKGPTL", R9A09G077_CLK_PCLKGPTL, CLK_SEL_CLK_PLL1, 2, 1),
> +       DEF_FIXED("PCLKH", R9A09G077_CLK_PCLKH, CLK_SEL_CLK_PLL1, 4, 1),
>         DEF_FIXED("PCLKM", R9A09G077_CLK_PCLKM, CLK_SEL_CLK_PLL1, 8, 1),
>         DEF_FIXED("PCLKL", R9A09G077_CLK_PCLKL, CLK_SEL_CLK_PLL1, 16, 1),
> +       DEF_FIXED("PCLKAH", R9A09G077_CLK_PCLKAH, CLK_PLL4D1, 6, 1),
>         DEF_FIXED("PCLKAM", R9A09G077_CLK_PCLKAM, CLK_PLL4D1, 12, 1),
>         DEF_FIXED("SDHI_CLKHS", R9A09G077_SDHI_CLKHS, CLK_SEL_CLK_PLL2, 1, 1),
>         DEF_FIXED("USB_CLK", R9A09G077_USB_CLK, CLK_PLL4D1, 48, 1),
> +       DEF_FIXED("ETCLKA", R9A09G077_ETCLKA, CLK_SEL_CLK_PLL1, 5, 1),
> +       DEF_FIXED("ETCLKB", R9A09G077_ETCLKB, CLK_SEL_CLK_PLL1, 8, 1),
> +       DEF_FIXED("ETCLKC", R9A09G077_ETCLKC, CLK_SEL_CLK_PLL1, 10, 1),
> +       DEF_FIXED("ETCLKD", R9A09G077_ETCLKD, CLK_SEL_CLK_PLL1, 20, 1),
> +       DEF_FIXED("ETCLKE", R9A09G077_ETCLKE, CLK_SEL_CLK_PLL1, 40, 1),
> +       DEF_FIXED("GMAC0_PCLKH", R9A09G077_GMAC0_PCLKH, R9A09G077_CLK_PCLKH, 1, 1),
> +       DEF_FIXED("GMAC1_PCLKH", R9A09G077_GMAC1_PCLKAH, R9A09G077_CLK_PCLKAH, 1, 1),
> +       DEF_FIXED("GMAC2_PCLKH", R9A09G077_GMAC2_PCLKAH, R9A09G077_CLK_PCLKAH, 1, 1),

Do you need these? I can't seem to find them in the documentation,
so they are not just for aiding the casual reader.  As their
multipliers/dividers are 1/1, you can just use R9A09G077_CLK_PCLKH
resp. R9A09G077_CLK_PCLKAH in the DTS?

>  };
>
>  static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
> @@ -181,7 +191,12 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
>         DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
>         DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
>         DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
> +       DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),
> +       DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),

According to Table 7.13 ("Overview of Clock Generation Circuit
Specifications (Internal Clock)"), ETCLKA is used as the operating
clock for ETHSW?

> +       DEF_MOD("ethss", 403, R9A09G077_CLK_PCLKM),
>         DEF_MOD("usb", 408, R9A09G077_CLK_PCLKAM),
> +       DEF_MOD("gmac1", 416, R9A09G077_CLK_PCLKAM),
> +       DEF_MOD("gmac2", 417, R9A09G077_CLK_PCLKAM),
>         DEF_MOD("sci5fck", 600, CLK_SCI5ASYNC),
>         DEF_MOD("iic2", 601, R9A09G077_CLK_PCLKL),
>         DEF_MOD("sdhi0", 1212, R9A09G077_CLK_PCLKAM),

The rest LGTM.  But as the full wiring is not clear to me, I guess
I'll have to wait for the DTS...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds