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Message-ID: <7b799cb3-ba9f-464e-a0a6-cad151742aab@altera.com>
Date: Tue, 2 Sep 2025 20:15:58 +0530
From: "G Thomas, Rohan" <rohan.g.thomas@...era.com>
To: "Russell King (Oracle)" <linux@...linux.org.uk>
Cc: Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>,
 "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>,
 Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
 netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
 Matthew Gerlach <matthew.gerlach@...era.com>
Subject: Re: [PATCH net-next] net: phy: marvell: Fix 88e1510 downshift counter
 errata

Hi Russell King,

Thanks for reviewing the patch.

On 9/2/2025 7:05 PM, Russell King (Oracle) wrote:
> On Tue, Sep 02, 2025 at 01:59:57PM +0800, Rohan G Thomas via B4 Relay wrote:
>> From: Rohan G Thomas <rohan.g.thomas@...era.com>
>>
>> The 88e1510 PHY has an erratum where the phy downshift counter is not
>> cleared on a link power down/up. This can cause the gigabit link to
>> intermittently downshift to a lower speed.
> 
> Does this apply to all 88e1510 PHYs or just some revisions?

I'm not entirely sure on this. But, based on 88E151x A0 "Errata and
Hardware Release Notes" from Marvell, no revision plans or fixes
mentioned for this issue but only the workaround is suggested for the
downshift feature. So, I think it is applicable for all 88e151x PHY
revisions.

> 
> Also, what is a "link power down/up" ? Are you referring to setting
> BMCR_PDOWN and then clearing it? (please update the commit description
> and repost after 24 hours, thanks.)
> 

Yes, I'm referring to setting and the clearing BMCR_PDOWN. Will update
the commit description in the next version.

Best Regards,
Rohan

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