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Message-ID:
 <DM4PR12MB6109780755A2328968922CB38C06A@DM4PR12MB6109.namprd12.prod.outlook.com>
Date: Tue, 2 Sep 2025 07:10:12 +0000
From: "Guntupalli, Manikanta" <manikanta.guntupalli@....com>
To: Alexandre Belloni <alexandre.belloni@...tlin.com>
CC: "git (AMD-Xilinx)" <git@....com>, "Simek, Michal" <michal.simek@....com>,
	"Frank.Li@....com" <Frank.Li@....com>, "robh@...nel.org" <robh@...nel.org>,
	"krzk+dt@...nel.org" <krzk+dt@...nel.org>, "conor+dt@...nel.org"
	<conor+dt@...nel.org>, "kees@...nel.org" <kees@...nel.org>,
	"gustavoars@...nel.org" <gustavoars@...nel.org>,
	"jarkko.nikula@...ux.intel.com" <jarkko.nikula@...ux.intel.com>,
	"linux-i3c@...ts.infradead.org" <linux-i3c@...ts.infradead.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-hardening@...r.kernel.org" <linux-hardening@...r.kernel.org>, "Pandey,
 Radhey Shyam" <radhey.shyam.pandey@....com>, "Goud, Srinivas"
	<srinivas.goud@....com>, "Datta, Shubhrajyoti" <shubhrajyoti.datta@....com>,
	"manion05gk@...il.com" <manion05gk@...il.com>
Subject: RE: [PATCH V2 2/2] i3c: master: Add AMD I3C bus controller driver

[AMD Official Use Only - AMD Internal Distribution Only]

Hi,

> -----Original Message-----
> From: Alexandre Belloni <alexandre.belloni@...tlin.com>
> Sent: Tuesday, September 2, 2025 1:43 AM
> To: Guntupalli, Manikanta <manikanta.guntupalli@....com>
> Cc: git (AMD-Xilinx) <git@....com>; Simek, Michal <michal.simek@....com>;
> Frank.Li@....com; robh@...nel.org; krzk+dt@...nel.org; conor+dt@...nel.org;
> kees@...nel.org; gustavoars@...nel.org; jarkko.nikula@...ux.intel.com; linux-
> i3c@...ts.infradead.org; devicetree@...r.kernel.org; linux-kernel@...r.kernel.org;
> linux-hardening@...r.kernel.org; Pandey, Radhey Shyam
> <radhey.shyam.pandey@....com>; Goud, Srinivas <srinivas.goud@....com>;
> Datta, Shubhrajyoti <shubhrajyoti.datta@....com>; manion05gk@...il.com
> Subject: Re: [PATCH V2 2/2] i3c: master: Add AMD I3C bus controller driver
>
> On 29/08/2025 22:43:27+0530, Manikanta Guntupalli wrote:
> > +static void xi3c_master_reset_fifos(struct xi3c_master *master) {
> > +   u32 data;
> > +
> > +   /* Reset fifos */
> > +   data = readl(master->membase + XI3C_RESET_OFFSET);
> > +   data |= XI3C_FIFOS_RST_MASK;
> > +   writel(data, master->membase + XI3C_RESET_OFFSET);
> > +   udelay(10);
>
> As pointed out by checkpatch:
> usleep_range is preferred over udelay, I guess it would be fine in this function.
In the error path, xi3c_master_reinit() gets called, which in turn calls xi3c_master_reset_fifos(). Since a spinlock is held at that point, we cannot sleep. Therefore, udelay() is used intentionally to avoid sleep.
>
> > +   data &= ~XI3C_FIFOS_RST_MASK;
> > +   writel(data, master->membase + XI3C_RESET_OFFSET);
> > +   udelay(10);
> > +}
> > +
>
> --

Thanks,
Manikanta.

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