linux-kernel - Re: [PATCH V2 2/2] i3c: master: Add AMD I3C bus controller driver

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Message-ID: <202509012012480348cc7a@mail.local>
Date: Mon, 1 Sep 2025 22:12:48 +0200
From: Alexandre Belloni <alexandre.belloni@...tlin.com>
To: Manikanta Guntupalli <manikanta.guntupalli@....com>
Cc: git@....com, michal.simek@....com, Frank.Li@....com, robh@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org, kees@...nel.org,
	gustavoars@...nel.org, jarkko.nikula@...ux.intel.com,
	linux-i3c@...ts.infradead.org, devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-hardening@...r.kernel.org,
	radhey.shyam.pandey@....com, srinivas.goud@....com,
	shubhrajyoti.datta@....com, manion05gk@...il.com
Subject: Re: [PATCH V2 2/2] i3c: master: Add AMD I3C bus controller driver

On 29/08/2025 22:43:27+0530, Manikanta Guntupalli wrote:
> +static void xi3c_master_reset_fifos(struct xi3c_master *master)
> +{
> +	u32 data;
> +
> +	/* Reset fifos */
> +	data = readl(master->membase + XI3C_RESET_OFFSET);
> +	data |= XI3C_FIFOS_RST_MASK;
> +	writel(data, master->membase + XI3C_RESET_OFFSET);
> +	udelay(10);

As pointed out by checkpatch:
usleep_range is preferred over udelay, I guess it would be fine in this
function.

> +	data &= ~XI3C_FIFOS_RST_MASK;
> +	writel(data, master->membase + XI3C_RESET_OFFSET);
> +	udelay(10);
> +}
> +

-- 
Alexandre Belloni, co-owner and COO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com