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Message-ID: <3160658ea2c4dd09a1d68918271177cf55437a8f.1756799774.git.michal.simek@amd.com>
Date: Tue, 2 Sep 2025 09:56:21 +0200
From: Michal Simek <michal.simek@....com>
To: <linux-kernel@...r.kernel.org>, <monstr@...str.eu>,
<michal.simek@...inx.com>, <git@...inx.com>
CC: Conor Dooley <conor+dt@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>, "open list:OPEN FIRMWARE
AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>, "moderated
list:ARM/ZYNQ ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH 4/4] arm64: zynqmp: Enable DP in kr260/kv260 revA
Enable DP output in both CC (Carrier Cards).
Signed-off-by: Michal Simek <michal.simek@....com>
---
.../boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso | 17 +++++++++++++++++
.../boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso | 17 +++++++++++++++++
2 files changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
index fbacfa984d76..b92dcb86e87e 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kr-g-revA.dtso
@@ -71,6 +71,17 @@ clk_25_1: si5332-4 { /* u17 - GEM3 */
#clock-cells = <0>;
clock-frequency = <25000000>;
};
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&i2c1 { /* I2C_SCK C26/C27 - MIO from SOM */
@@ -145,6 +156,12 @@ &zynqmp_dpsub {
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
+
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
index 3c36eb52e968..d7351a17d3e8 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-sck-kv-g-revA.dtso
@@ -72,6 +72,17 @@ si5332_5: si5332-5 { /* u17 */
#clock-cells = <0>;
clock-frequency = <27000000>;
};
+ dpcon {
+ compatible = "dp-connector";
+ label = "P11";
+ type = "full-size";
+
+ port {
+ dpcon_in: endpoint {
+ remote-endpoint = <&dpsub_dp_out>;
+ };
+ };
+ };
};
&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
@@ -122,6 +133,12 @@ &zynqmp_dpsub {
assigned-clock-rates = <27000000>, <25000000>, <300000000>;
};
+&out_dp {
+ dpsub_dp_out: endpoint {
+ remote-endpoint = <&dpcon_in>;
+ };
+};
+
&zynqmp_dpdma {
status = "okay";
assigned-clock-rates = <600000000>;
--
2.43.0
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