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Message-ID: <20250902075548.1967613-4-valentina.fernandezalanis@microchip.com>
Date: Tue, 2 Sep 2025 08:55:46 +0100
From: Valentina Fernandez <valentina.fernandezalanis@...rochip.com>
To: <conor.dooley@...rochip.com>, <daire.mcnamara@...rochip.com>,
<paul.walmsley@...ive.com>, <palmer@...belt.com>, <robh@...nel.org>,
<krzk+dt@...nel.org>, <aou@...s.berkeley.edu>, <alex@...ti.fr>,
<valentina.fernandezalanis@...rochip.com>
CC: <linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<devicetree@...r.kernel.org>
Subject: [PATCH v2 3/5] riscv: dts: microchip: add icicle kit with production device
With the introduction of the Icicle Kit using the production MPFS250T
device, it's necessary to distinguish it from the engineering sample
(-es) variant. Engineering samples cannot write to flash from the MSS,
as noted in the PolarFire SoC FPGA ES errata.
Add a new device tree (mpfs-icicle-kit-prod.dts) for the production
board which includes the icicle kit common dtsi and enable the system
controller SPI flash, which is only accessible on production silicon.
Remove redundant board compatible from fabric dtsi and update board
compatibles for v2025.07 release, which includes Mi-V IHC v2 for AMP
cluster communication.
Fix formatting by using lowecase hex everywhere and remove reduntant
status properties from common dtsi.
Signed-off-by: Valentina Fernandez <valentina.fernandezalanis@...rochip.com>
---
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-icicle-kit-common.dtsi | 10 ++++----
.../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 23 ++++++++++++++++---
.../dts/microchip/mpfs-icicle-kit-prod.dts | 23 +++++++++++++++++++
.../boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++-
5 files changed, 52 insertions(+), 8 deletions(-)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile
index f51aeeb9fd3b..1e2f4e41bf0d 100644
--- a/arch/riscv/boot/dts/microchip/Makefile
+++ b/arch/riscv/boot/dts/microchip/Makefile
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
+dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit-prod.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
index eafea3b69cd7..e01a216e6c3a 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-common.dtsi
@@ -53,13 +53,11 @@ led-4 {
ddrc_cache_lo: memory@...00000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
- status = "okay";
};
ddrc_cache_hi: memory@...0000000 {
device_type = "memory";
reg = <0x10 0x40000000 0x0 0x40000000>;
- status = "okay";
};
reserved-memory {
@@ -67,8 +65,8 @@ reserved-memory {
#size-cells = <2>;
ranges;
- hss_payload: region@...00000 {
- reg = <0x0 0xBFC00000 0x0 0x400000>;
+ hss_payload: region@...00000 {
+ reg = <0x0 0xbfc00000 0x0 0x400000>;
no-map;
};
};
@@ -134,6 +132,10 @@ &i2c2 {
status = "okay";
};
+&ihc {
+ status = "okay";
+};
+
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
index a6dda55a2d1d..e673b676fd1a 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
@@ -2,9 +2,6 @@
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/ {
- compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
- "microchip,mpfs";
-
core_pwm0: pwm@...00000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x40000000 0x0 0xF0>;
@@ -26,6 +23,26 @@ i2c2: i2c@...00200 {
status = "disabled";
};
+ ihc: mailbox {
+ compatible = "microchip,sbi-ipc";
+ interrupt-parent = <&plic>;
+ interrupts = <180>, <179>, <178>, <177>;
+ interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ mailbox@...00000 {
+ compatible = "microchip,miv-ihc-rtl-v2";
+ reg = <0x0 0x50000000 0x0 0x1c000>;
+ interrupt-parent = <&plic>;
+ interrupts = <180>, <179>, <178>, <177>;
+ interrupt-names = "hart-1", "hart-2", "hart-3", "hart-4";
+ #mbox-cells = <1>;
+ microchip,ihc-chan-disabled-mask = /bits/ 16 <0>;
+ status = "disabled";
+ };
+
pcie: pcie@...0000000 {
compatible = "microchip,pcie-host-1.0";
#address-cells = <0x3>;
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
new file mode 100644
index 000000000000..8afedece89d1
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-prod.dts
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2025 Microchip Technology Inc */
+
+/dts-v1/;
+
+#include "mpfs-icicle-kit-common.dtsi"
+
+/ {
+ model = "Microchip PolarFire-SoC Icicle Kit (Production Silicon)";
+ compatible = "microchip,mpfs-icicle-prod-reference-rtl-v2507",
+ "microchip,mpfs-icicle-kit-prod",
+ "microchip,mpfs-icicle-kit",
+ "microchip,mpfs-prod",
+ "microchip,mpfs";
+};
+
+&syscontroller {
+ microchip,bitstream-flash = <&sys_ctrl_flash>;
+};
+
+&syscontroller_qspi {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 2cb08ed0946d..556aa9638282 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -7,6 +7,7 @@
/ {
model = "Microchip PolarFire-SoC Icicle Kit";
- compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+ compatible = "microchip,mpfs-icicle-es-reference-rtl-v2507",
+ "microchip,mpfs-icicle-kit",
"microchip,mpfs";
};
--
2.34.1
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