linux-kernel - Re: [PATCH 5/5] arm64: tegra: Limit max cpu frequency on P3450

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Message-ID: <7006329.Sb9uPGUboI@senjougahara>
Date: Wed, 03 Sep 2025 14:50:37 +0900
From: Mikko Perttunen <mperttunen@...dia.com>
To: Michael Turquette <mturquette@...libre.com>,
 Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
 Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
 Thierry Reding <thierry.reding@...il.com>,
 Jonathan Hunter <jonathanh@...dia.com>, Joseph Lo <josephl@...dia.com>,
 Peter De Schrijver <pdeschrijver@...dia.com>,
 Prashant Gaikwad <pgaikwad@...dia.com>, webgeek1234@...il.com
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
 linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org,
 Thierry Reding <treding@...dia.com>, Aaron Kling <webgeek1234@...il.com>
Subject: Re: [PATCH 5/5] arm64: tegra: Limit max cpu frequency on P3450

On Saturday, August 16, 2025 2:53 PM Aaron Kling via B4 Relay wrote:
> From: Aaron Kling <webgeek1234@...il.com>
> 
> P3450's cpu is only rated for 1.4 GHz while the CVB table it uses tries
> to scale to 1.5 GHz. Set an appropriate limit on the maximum scaling
> frequency.

Looking at downstream, from what I can tell, the CPU's maximum frequency is indeed 1.55GHz under normal conditions. However, at temperatures over 90C, its voltage is limited to 1090mV. Reference:

static struct dvfs_therm_limits
tegra210_core_therm_caps_ucm2[MAX_THERMAL_LIMITS] = {
        {86, 1090},
        {0, 0},
};
(rel-32 kernel-4.9/drivers/soc/tegra/tegra210-dvfs.c)

Here the throttling is set at 86C, I suppose to give some margin.

1090mV perfectly matches the 1.479GHz operating point defined in the upstream kernel. So it seems to me that rather than setting a maximum frequency, we would need temperature dependent DVFS. Or, at least as a first step, we could have the driver just always limit the maximum frequency so it fits under the thermal cap voltage -- the temperature limit is rather high, after all.

If you have other information, please do tell.

Incidentally, some of the CVB tables in the upstream kernel seem to ignore speedo (I assume they are conservative) while rel-32 has different tables. So the upstream kernel is probably running at slightly unnecessarily high voltages.

Cheers,
Mikko

> 
> Signed-off-by: Aaron Kling <webgeek1234@...il.com>
> ---
>  arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
> index ec0e84cb83ef9bf8f0e52e2958db33666813917c..10f878d3f50815d1f0297d15669048ab9cad73ee 100644
> --- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
> +++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
> @@ -594,6 +594,7 @@ clock@...10000 {
>  		nvidia,droop-ctrl = <0x00000f00>;
>  		nvidia,force-mode = <1>;
>  		nvidia,sample-rate = <25000>;
> +		nvidia,dfll-max-freq = <1479000000>;
>  
>  		nvidia,pwm-min-microvolts = <708000>;
>  		nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
> 
>