linux-kernel - Re: [PATCH v2 2/2] clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks

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Message-ID: <CAMuHMdWN=ofULw+TZVA6eY3hAyaiKMN6z2Z57KH=EDUzxbDf1A@mail.gmail.com>
Date: Wed, 3 Sep 2025 11:03:49 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, linux-renesas-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
	devicetree@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH v2 2/2] clk: renesas: r9a09g077: Add Ethernet Subsystem
 core and module clocks

Hi Prabhakar,

On Tue, 2 Sept 2025 at 17:06, Lad, Prabhakar <prabhakar.csengg@...il.com> wrote:
> On Tue, Sep 2, 2025 at 2:01 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > On Mon, 1 Sept 2025 at 20:30, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Add module and core clocks used by Ethernet Subsystem (Ethernet_SS),
> > > Ethernet MAC (GMAC), Ethernet Switch (ETHSW).
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >
> > > --- a/drivers/clk/renesas/r9a09g077-cpg.c
> > > +++ b/drivers/clk/renesas/r9a09g077-cpg.c
> > > @@ -181,7 +191,12 @@ static const struct mssr_mod_clk r9a09g077_mod_clks[] __initconst = {
> > >         DEF_MOD("sci4fck", 12, CLK_SCI4ASYNC),
> > >         DEF_MOD("iic0", 100, R9A09G077_CLK_PCLKL),
> > >         DEF_MOD("iic1", 101, R9A09G077_CLK_PCLKL),
> > > +       DEF_MOD("gmac0", 400, R9A09G077_CLK_PCLKM),
> > > +       DEF_MOD("ethsw", 401, R9A09G077_CLK_PCLKM),
> >
> > According to Table 7.13 ("Overview of Clock Generation Circuit
> > Specifications (Internal Clock)"), ETCLKA is used as the operating
> > clock for ETHSW?
> >
> There are 3 clock inputs to ETHSW,
> - PCLKM -  bus clock
> - ETCLKA - operating clock
> - ETCLKB - Ts clock
>
> Based on Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml
> we have two clocks for RZ/N1 (Ts clock is missing)
> - description: AHB clock used for the switch register interface
> - description: Switch system clock
>
> - const: hclk
> - const: clk
>
> So I was treating,
> - hclk -> PCLKM,
> - clk   -> ETCLKA
> - ts    -> ETCLKB
>
> Since pclkm is used for register access, I added this entry to the
> r9a09g077_mod_clks array as I was under the impression the clocks used
> for reg access need to go into this array.

OK, thanks for the explanation!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds