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Message-ID: <0a64efe5-9b07-4188-be30-54f268e862bf@baylibre.com>
Date: Thu, 4 Sep 2025 09:15:19 -0500
From: David Lechner <dlechner@...libre.com>
To: Jonathan Cameron <jic23@...nel.org>
Cc: Michael Hennerich <Michael.Hennerich@...log.com>,
Nuno Sá <nuno.sa@...log.com>,
Andy Shevchenko <andy@...nel.org>, linux-iio@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH] iio: adc: ad7124: fix sample rate for multi-channel use
On 9/1/25 10:57 AM, Jonathan Cameron wrote:
> On Thu, 28 Aug 2025 11:42:28 -0500
> David Lechner <dlechner@...libre.com> wrote:
...
>> @@ -261,8 +263,12 @@ static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel
>> * fCLK is the master clock frequency
>> * FS[10:0] are the bits in the filter register
>> * FS[10:0] can have a value from 1 to 2047
>> + * When multiple channels in the sequencer or the SINGLE_CYCLE bit is
> This sentence doesn't read. Maybe something with a few more words like.
>
> * When multiple channels are enabled in the sequencer, the
> * SINGLE_CYCLE bit is set or when certain filter modes are enabled,...
>
>> + * or when certain filter modes are enabled, there is an extra factor
>> + * of (4 + AVG - 1) to allow for settling time.
* When multiple channels are enabled in the sequencer, the SINGLE_CYCLE
* bit is set, or when a fast settling filter mode is enabled on any
* channel, there is an extra factor of (4 + AVG - 1) to allow for
* settling time. We ensure that at least one of these is always true so
* that we always use the same factor.
>> */
>> - odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
>> + factor = 32 * (4 + avg - 1);
>> + odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * factor);
>
>
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