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Message-Id: <175700498544.244191.11713819385906991702.b4-ty@kernel.org>
Date: Thu, 04 Sep 2025 22:26:25 +0530
From: Manivannan Sadhasivam <mani@...nel.org>
To: andersson@...nel.org, konradybcio@...nel.org, robh@...nel.org, 
 krzk+dt@...nel.org, conor+dt@...nel.org, jingoohan1@...il.com, 
 lpieralisi@...nel.org, kwilczynski@...nel.org, bhelgaas@...gle.com, 
 johan+linaro@...nel.org, vkoul@...nel.org, kishon@...nel.org, 
 neil.armstrong@...aro.org, abel.vesa@...aro.org, 
 Krzysztof WilczyƄski <kwilczynski@...nel.org>, 
 Ziyue Zhang <ziyue.zhang@....qualcomm.com>
Cc: linux-arm-msm@...r.kernel.org, devicetree@...r.kernel.org, 
 linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org, 
 linux-phy@...ts.infradead.org, qiang.yu@....qualcomm.com, 
 quic_krichai@...cinc.com, quic_vbadigan@...cinc.com
Subject: Re: (subset) [PATCH v6 0/3] Add Equalization Settings for 8.0 GT/s
 and 32.0 GT/s and Add PCIe Lane Equalization Preset Properties for 8.0
 GT/s and 16.0 GT/s


On Thu, 04 Sep 2025 14:52:22 +0800, Ziyue Zhang wrote:
> This series adds add equalization settings for 8.0 GT/s and 32.0 GT/s,
> and add PCIe lane equalization preset properties for 8.0 GT/s and
> 16.0 GT/s for sa8775p ride platform, which fix AER errors.
> 
> While equalization settings for 16 GT/s have already been set, this
> update adds the required equalization settings for PCIe operating at
> 8.0 GT/s and 32.0 GT/s, including the configuration of shadow registers,
> ensuring optimal performance and stability.
> 
> [...]

Applied, thanks!

[1/3] PCI: qcom: Add equalization settings for 8.0 GT/s and 32.0 GT/s
      commit: 37bf0f4e39de9b53bc6f8d3702b021e2c6b5bae3
[2/3] PCI: qcom: fix macro typo for CURSOR
      commit: ea5fbbc15906abdef174c88cecfec4b2a0c748b9

Best regards,
-- 
Manivannan Sadhasivam <mani@...nel.org>


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