[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20250904082151.2929189-3-h-shenoy@ti.com>
Date: Thu, 4 Sep 2025 13:51:50 +0530
From: Harikrishna Shenoy <h-shenoy@...com>
To: <vkoul@...nel.org>, <kishon@...nel.org>, <devarsht@...com>,
<tomi.valkeinen@...asonboard.com>, <aradhya.bhatia@...ux.dev>,
<u.kleine-koenig@...libre.com>, <mripard@...nel.org>,
<sakari.ailus@...ux.intel.com>, <linux-phy@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <u-kumar1@...com>, <s-jain1@...com>
Subject: [PATCH RESEND 2/3] phy: cadence: cdns-dphy: Update calibration wait time for startup state machine
From: Devarsh Thakkar <devarsht@...com>
Do read-modify-write so that we re-use the characterized reset value as
specified in TRM [1] to program calibration wait time which defines number
of cycles to wait for after startup state machine is in bandgap enable
state.
This fixes PLL lock timeout error faced while using RPi DSI Panel on TI's
AM62L and J721E SoC since earlier calibration wait time was getting
overwritten to zero value thus failing the PLL to lockup and causing
timeout.
[1] AM62P TRM (Section 14.8.6.3.2.1.1 DPHY_TX_DPHYTX_CMN0_CMN_DIG_TBIT2):
Link: https://www.ti.com/lit/pdf/spruj83
Cc: stable@...r.kernel.org
Fixes: 7a343c8bf4b5 ("phy: Add Cadence D-PHY support")
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@...asonboard.com>
Signed-off-by: Devarsh Thakkar <devarsht@...com>
Tested-by: Harikrishna Shenoy <h-shenoy@...com>
Signed-off-by: Harikrishna Shenoy <h-shenoy@...com>
---
Rebased on top of linux-next and resend.
Link to original patch- https://lore.kernel.org/all/20250704125915.1224738-3-devarsht@ti.com/
drivers/phy/cadence/cdns-dphy.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/cdns-dphy.c b/drivers/phy/cadence/cdns-dphy.c
index da8de0a9d086..24a25606996c 100644
--- a/drivers/phy/cadence/cdns-dphy.c
+++ b/drivers/phy/cadence/cdns-dphy.c
@@ -30,6 +30,7 @@
#define DPHY_CMN_SSM DPHY_PMA_CMN(0x20)
#define DPHY_CMN_SSM_EN BIT(0)
+#define DPHY_CMN_SSM_CAL_WAIT_TIME GENMASK(8, 1)
#define DPHY_CMN_TX_MODE_EN BIT(9)
#define DPHY_CMN_PWM DPHY_PMA_CMN(0x40)
@@ -410,7 +411,8 @@ static int cdns_dphy_power_on(struct phy *phy)
writel(reg, dphy->regs + DPHY_BAND_CFG);
/* Start TX state machine. */
- writel(DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
+ reg = readl(dphy->regs + DPHY_CMN_SSM);
+ writel((reg & DPHY_CMN_SSM_CAL_WAIT_TIME) | DPHY_CMN_SSM_EN | DPHY_CMN_TX_MODE_EN,
dphy->regs + DPHY_CMN_SSM);
ret = cdns_dphy_wait_for_pll_lock(dphy);
--
2.34.1
Powered by blists - more mailing lists