[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-ID: <20250904082151.2929189-1-h-shenoy@ti.com>
Date: Thu, 4 Sep 2025 13:51:48 +0530
From: Harikrishna Shenoy <h-shenoy@...com>
To: <vkoul@...nel.org>, <kishon@...nel.org>, <devarsht@...com>,
<tomi.valkeinen@...asonboard.com>, <aradhya.bhatia@...ux.dev>,
<u.kleine-koenig@...libre.com>, <mripard@...nel.org>,
<sakari.ailus@...ux.intel.com>, <linux-phy@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>, <u-kumar1@...com>, <s-jain1@...com>
Subject: [PATCH RESEND 0/3] Fix and optimize cadence DPHY driver
This series optimizes the cadence dphy driver by below improvements:
- Fixes PLL lockup and O_CMN_READY timeout by moving the polling
function after common state machine gets enabled. Also fix the
calibration wait time to optimize the polling time.
- Enable support for data lane rates between 80-160 Mbps,
enables lower resolutions like 640x480 at 60Hz.
Series is a combination of below 2 series, rebased on top of next-20250901:
- https://lore.kernel.org/all/20250704125915.1224738-1-devarsht@ti.com/
- https://lore.kernel.org/all/20250807052002.717807-1-h-shenoy@ti.com/
Devarsh Thakkar (2):
phy: cadence: cdns-dphy: Fix PLL lock and O_CMN_READY polling
phy: cadence: cdns-dphy: Update calibration wait time for startup
state machine
Harikrishna Shenoy (1):
drivers: phy: cadence: cdns-dphy: Enable lower resolutions in dphy
drivers/phy/cadence/cdns-dphy.c | 130 ++++++++++++++++++++++++--------
1 file changed, 97 insertions(+), 33 deletions(-)
--
2.34.1
Powered by blists - more mailing lists