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Message-ID: <CAJM55Z9KJNPOp1ngDqKz0BDpxWu-_cqOMALSE_Jou9FU2TPK9g@mail.gmail.com>
Date: Thu, 4 Sep 2025 02:02:22 -0700
From: Emil Renner Berthing <emil.renner.berthing@...onical.com>
To: E Shattow <e@...eshell.de>, Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>
Cc: linux-riscv@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Hal Feng <hal.feng@...rfivetech.com>,
Minda Chen <minda.chen@...rfivetech.com>
Subject: Re: [PATCH v3 RESEND 0/3] riscv: dts: starfive: jh7110: More U-Boot
downstream changes for JH7110
E Shattow wrote:
> Bring in additional downstream U-Boot boot loader changes for StarFive
> VisionFive2 board target (and related JH7110 common boards). Create a
> basic dt-binding (and not any Linux driver) in support of the
> memory-controller dts node used in mainline U-Boot. Also add
> bootph-pre-ram hinting to jh7110.dtsi needed at SPL boot phase.
>
> Changes since v2:
>
> - patch 1/3 "add StarFive JH7110 SoC DMC": wrap at 80 col, clock-names
> const is 'pll'.
>
> - patch 2/3 "add memory controller node": memory-controller node follows
> sorting style by reg address, between watchdog and crypto nodes. Update
> clock-names to 'pll'.
>
> - patch 3/3 "bootph-pre-ram hinting needed by boot loader": add missing
> hints for syscrg dependencies 'gmac1_rgmii_rxin', 'gmac1_rmii_refin',
> and 'pllclk'.
>
> E Shattow (3):
> dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
> riscv: dts: starfive: jh7110: add DMC memory controller
> riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot
> loader
>
> .../starfive,jh7110-dmc.yaml | 74 +++++++++++++++++++
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 24 ++++++
> 2 files changed, 98 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml
Thank you!
For the whole series:
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@...onical.com>
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