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Message-ID: <20250905132328.9859-2-cn.liweihao@gmail.com>
Date: Fri, 5 Sep 2025 21:23:25 +0800
From: WeiHao Li <cn.liweihao@...il.com>
To: heiko@...ech.de,
robh@...nel.org
Cc: krzk+dt@...nel.org,
conor+dt@...nel.org,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org,
WeiHao Li <cn.liweihao@...il.com>
Subject: [PATCH v1 1/4] clk: rockchip: rk3368: fix SCLK_I2S_8CH_OUT flags
Clock SCLK_I2S_8CH_OUT has no capability to adjust clock frequency by
itself, add CLK_SET_RATE_PARENT flag to fix it.
Signed-off-by: WeiHao Li <cn.liweihao@...il.com>
---
drivers/clk/rockchip/clk-rk3368.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 95e6996adb..8159f643dc 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -371,7 +371,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
RK3368_CLKSEL_CON(28), 0,
RK3368_CLKGATE_CON(6), 2, GFLAGS,
&rk3368_i2s_8ch_fracmux),
- COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, 0,
+ COMPOSITE_NODIV(SCLK_I2S_8CH_OUT, "i2s_8ch_clkout", mux_i2s_8ch_clkout_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(27), 15, 1, MFLAGS,
RK3368_CLKGATE_CON(6), 0, GFLAGS),
GATE(SCLK_I2S_8CH, "sclk_i2s_8ch", "i2s_8ch_pre", CLK_SET_RATE_PARENT,
--
2.39.5
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