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Message-ID: <20250905132328.9859-4-cn.liweihao@gmail.com>
Date: Fri, 5 Sep 2025 21:23:27 +0800
From: WeiHao Li <cn.liweihao@...il.com>
To: heiko@...ech.de,
robh@...nel.org
Cc: krzk+dt@...nel.org,
conor+dt@...nel.org,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org,
WeiHao Li <cn.liweihao@...il.com>
Subject: [PATCH v1 3/4] clk: rockchip: rk3368: use clock ids CLK_I2S_8CH_PRE and CLK_I2S_8CH_FRAC
Export the clocks via the newly added clock-ids.
Signed-off-by: WeiHao Li <cn.liweihao@...il.com>
---
drivers/clk/rockchip/clk-rk3368.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 8159f643dc..1fb18c9596 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -244,7 +244,7 @@ static struct rockchip_cpuclk_rate_table rk3368_cpuclkl_rates[] __initdata = {
};
static struct rockchip_clk_branch rk3368_i2s_8ch_fracmux __initdata =
- MUX(0, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
+ MUX(CLK_I2S_8CH_PRE, "i2s_8ch_pre", mux_i2s_8ch_pre_p, CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(27), 8, 2, MFLAGS);
static struct rockchip_clk_branch rk3368_spdif_8ch_fracmux __initdata =
@@ -367,7 +367,7 @@ static struct rockchip_clk_branch rk3368_clk_branches[] __initdata = {
COMPOSITE(0, "i2s_8ch_src", mux_pll_src_cpll_gpll_p, 0,
RK3368_CLKSEL_CON(27), 12, 1, MFLAGS, 0, 7, DFLAGS,
RK3368_CLKGATE_CON(6), 1, GFLAGS),
- COMPOSITE_FRACMUX(0, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
+ COMPOSITE_FRACMUX(CLK_I2S_8CH_FRAC, "i2s_8ch_frac", "i2s_8ch_src", CLK_SET_RATE_PARENT,
RK3368_CLKSEL_CON(28), 0,
RK3368_CLKGATE_CON(6), 2, GFLAGS,
&rk3368_i2s_8ch_fracmux),
--
2.39.5
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