linux-kernel - Re: [PATCH v1 2/2] iio: adc: Add the NXP SAR ADC support for the s32g2/3 platforms

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Message-ID: <c23ed0cf-8188-49ac-b310-57bbfb54f337@baylibre.com>
Date: Mon, 8 Sep 2025 08:58:49 -0500
From: David Lechner <dlechner@...libre.com>
To: Daniel Lezcano <daniel.lezcano@...aro.org>,
 Nuno Sá <noname.nuno@...il.com>, jic23@...nel.org,
 nuno.sa@...log.com, andy@...nel.org, robh@...nel.org, conor+dt@...nel.org,
 krzk+dt@...nel.org
Cc: linux-iio@...r.kernel.org, s32@....com, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org, chester62515@...il.com, mbrugger@...e.com,
 ghennadi.procopciuc@....nxp.com
Subject: Re: [PATCH v1 2/2] iio: adc: Add the NXP SAR ADC support for the
 s32g2/3 platforms

On 9/8/25 7:16 AM, Daniel Lezcano wrote:
> On 05/09/2025 23:54, David Lechner wrote:
>> On 9/5/25 3:58 PM, Daniel Lezcano wrote:
>>> On 05/09/2025 17:25, David Lechner wrote:
>>>> On 9/5/25 4:44 AM, Daniel Lezcano wrote:
>>>>> On 04/09/2025 19:49, David Lechner wrote:
>>>>>> On 9/4/25 12:40 PM, Daniel Lezcano wrote:
>>>
>>> [ ... ]
>>>
>>>> Taking a step back, what sort of real-world uses cases do you need to support?
>>>> Or are you just trying to implement everything that the ADC can do? The latter
>>>> can be a bit risky because you might end making something where you can't do
>>>> a buffered read and a single channel read at the same time, but later find out
>>>> you have a real-world application that needs to do this.
>>>>
>>>> It looks like it would be possible to implement buffered reads in lots of ways.
>>>> IIO devices can have more than one buffer per device so we can add more in the
>>>> future if we need to. So I would just drop the DMA part of the implementation
>>>> for now and implement the basic triggered buffer using MCR[NSTART] and ECH
>>>> (End of Chain) interrupt request and just reading data from the ICDR registers.
>>>>
>>>> I would wait to have a real-world application that requires DMA to decide the
>>>> best way to implement that. There are lots of possibilities, like does it need
>>>> an external trigger or is continuous mode good enough? Does it need to be cyclic
>>>> (something the IIO subsystem doesn't really support yet) or not. Is exact sample
>>>> timing important or do we just need a big buffer? These questions we can't
>>>> really answer without a specific application to use it.
>>>
>>> In the case of this IP, the use cases are in the automotive context. The system running on the APU is supposed to monitor at high rate (or not) the different channels which can be connected to any device the integrator choose to use.
>>>
>>> For this reason, the driver should be able to support the different modes because the integrator of the car computer can decide to monitor the devices connected to the different channels differently.
>>>
>>> Said differently, we need these modes because the capture depends on what the integrator decide to connect to the different channels.
>> ...
>>> We just know all these use cases exist.
> 
> 
> The submitted driver supports the three modes.
> 
> Nuno asked to use the IIO dma engine API.
> 
> However there is few information and examples with the API and I failed to use the devm_iio_dmaengine_buffer_setup_with_handle() function.
> 
> AFAICT, devm_iio_dmaengine_buffer_setup_ext() can not be used because dma_slave_config() is not called, thus the src_addr is not set.
> 
> Is there any example somewhere, documentation or guidance to use the API?
> 
> Thanks
> 
>   -- Daniel
> 
> 

Unfortunately, not really. Until the last few years, there wasn't really
any users of these APIs. I added devm_iio_dmaengine_buffer_setup_with_handle()
for the SPI offloading work I did recently. The only reason it had to be
added is because we needed to get the DMA handle from a different devicetree
node from the ADC's node. Since this device has dmas and dma-names in
the devicetree, then if devm_iio_dmaengine_buffer_setup[_ext]() doesn't work
with that, then it might have other problems (assumptions made for a specific
use case) than just not calling dma_slave_config().

I think maybe Nuno and certainly I are guilty of trying to offer you advice
without looking deeply enough into what you already submitted. :-/

I see now that what you are doing with the DMA looks more like other SoC ADCs
(AT91/STM32/AM335x) which is quite different from how the iio_dmaengine_buffer
stuff works, e.g. cyclic vs. not. So unless you are interested in evolving
the iio_dmaengine_buffer code to be more general to handle this case as well,
it might not be the right tool for the job currently.