linux-kernel - Re: [PATCH] pinctrl: airoha: fix wrong MDIO function bitmaks

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Message-ID: <68bf2b2d.050a0220.7d5a6.b11c@mx.google.com>
Date: Mon, 8 Sep 2025 21:14:49 +0200
From: Christian Marangi <ansuelsmth@...il.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: Lorenzo Bianconi <lorenzo@...nel.org>, Sean Wang <sean.wang@...nel.org>,
	Linus Walleij <linus.walleij@...aro.org>,
	Matthias Brugger <matthias.bgg@...il.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	Benjamin Larsson <benjamin.larsson@...exis.eu>,
	linux-mediatek@...ts.infradead.org, linux-gpio@...r.kernel.org,
	linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
	stable@...r.kernel.org
Subject: Re: [PATCH] pinctrl: airoha: fix wrong MDIO function bitmaks

On Mon, Sep 08, 2025 at 09:06:03PM +0200, Andrew Lunn wrote:
> On Mon, Sep 08, 2025 at 07:48:17PM +0200, Christian Marangi wrote:
> > On Mon, Sep 08, 2025 at 06:54:15PM +0200, Andrew Lunn wrote:
> > > On Mon, Sep 08, 2025 at 01:37:19PM +0200, Christian Marangi wrote:
> > > > With further testing with an attached Aeonsemi it was discovered that
> > > > the pinctrl MDIO function applied the wrong bitmask. The error was
> > > > probably caused by the confusing documentation related to these bits.
> > > > 
> > > > Inspecting what the bootloader actually configure, the SGMII_MDIO_MODE
> > > > is never actually set but instead it's set force enable to the 2 GPIO
> > > > (gpio 1-2) for MDC and MDIO pin.
> > > 
> > > Is the MDIO bus implemented using the GPIO bitbanging driver?
> > > 
> > 
> > No it does use the MDIO bus integrated in the MT7530 Switch. It's just
> > that the MDIO pin can be muxed as GPIO usage.
> 
> Then i do not understand this patch. Why configure the pinmux for GPIO
> when you want it connected to the MDIO bus device?
>

The usage of GPIO might be confusing but this is just to instruct the
SoC to not mess with those 2 PIN and as Benjamin reported it's also an
Errata of 7581. The FORCE_GPIO_EN doesn't set them as GPIO function
(that is configured by a different register) but it's really to actually
""enable"" those lines.

Normally the SoC should autodetect this by HW but it seems AN7581 have
problem with this and require this workaround to force enable the 2 pin.

-- 
	Ansuel