linux-kernel - Re: [PATCH 1/1] phy: rockchip: naneng-combphy: use existing DT property check for rk3528

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Message-ID: <aMFyp1pn5xUJOVtj@pie>
Date: Wed, 10 Sep 2025 12:44:23 +0000
From: Yao Zi <ziyao@...root.org>
To: Chukun Pan <amadeus@....edu.cn>, Vinod Koul <vkoul@...nel.org>
Cc: Heiko Stuebner <heiko@...ech.de>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	linux-arm-kernel@...ts.infradead.org,
	linux-rockchip@...ts.infradead.org, linux-phy@...ts.infradead.org,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/1] phy: rockchip: naneng-combphy: use existing DT
 property check for rk3528

On Wed, Sep 10, 2025 at 08:20:00PM +0800, Chukun Pan wrote:
> The naneng-combphy driver already has DT property checks for
> "rockchip,enable-ssc" and "rockchip,ext-refclk", use it for
> the rk3528_combphy_cfg. Also aligned the indentation of the
> rk3528_combphy_grfcfgs parameters (using tabs).
> 
> Signed-off-by: Chukun Pan <amadeus@....edu.cn>
> ---
>  drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)

I should have noticed this simplification. Thanks for following up,

Reviewed-by: Yao Zi <ziyao@...root.org>

> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index a3ef19807b9e..ad6c8a11951b 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -518,7 +518,7 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		return -EINVAL;
>  	}
>  
> -	if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
> +	if (priv->ext_refclk) {
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
>  
>  		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> @@ -543,11 +543,9 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		}
>  	}
>  
> -	if (priv->type == PHY_TYPE_PCIE) {
> -		if (device_property_read_bool(priv->dev, "rockchip,enable-ssc"))
> -			rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
> -						 RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
> -	}
> +	if (priv->type == PHY_TYPE_PCIE && priv->enable_ssc)
> +		rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
> +					 RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
>  
>  	return 0;
>  }
> @@ -571,7 +569,7 @@ static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
>  	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x101 },
>  	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
>  	/* pipe-grf */
> -	.u3otg0_port_en         = { 0x0044, 15, 0, 0x0181, 0x1100 },
> +	.u3otg0_port_en		= { 0x0044, 15, 0, 0x0181, 0x1100 },
>  };
>  
>  static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
> -- 
> 2.25.1
>