linux-kernel - Re: [PATCH 1/1] phy: rockchip: naneng-combphy: use existing DT property check for rk3528

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <2049032.8hb0ThOEGa@diego>
Date: Thu, 11 Sep 2025 10:55:17 +0200
From: Heiko Stübner <heiko@...ech.de>
To: Vinod Koul <vkoul@...nel.org>, Chukun Pan <amadeus@....edu.cn>
Cc: Yao Zi <ziyao@...root.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
 linux-arm-kernel@...ts.infradead.org, linux-rockchip@...ts.infradead.org,
 linux-phy@...ts.infradead.org, linux-kernel@...r.kernel.org,
 Chukun Pan <amadeus@....edu.cn>
Subject:
 Re: [PATCH 1/1] phy: rockchip: naneng-combphy: use existing DT property check
 for rk3528

Am Mittwoch, 10. September 2025, 14:20:00 Mitteleuropäische Sommerzeit schrieb Chukun Pan:
> The naneng-combphy driver already has DT property checks for
> "rockchip,enable-ssc" and "rockchip,ext-refclk", use it for
> the rk3528_combphy_cfg. Also aligned the indentation of the
> rk3528_combphy_grfcfgs parameters (using tabs).
> 
> Signed-off-by: Chukun Pan <amadeus@....edu.cn>

Reviewed-by: Heiko Stuebner <heiko@...ech.de>

> ---
>  drivers/phy/rockchip/phy-rockchip-naneng-combphy.c | 12 +++++-------
>  1 file changed, 5 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> index a3ef19807b9e..ad6c8a11951b 100644
> --- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> +++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
> @@ -518,7 +518,7 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		return -EINVAL;
>  	}
>  
> -	if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
> +	if (priv->ext_refclk) {
>  		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
>  
>  		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
> @@ -543,11 +543,9 @@ static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
>  		}
>  	}
>  
> -	if (priv->type == PHY_TYPE_PCIE) {
> -		if (device_property_read_bool(priv->dev, "rockchip,enable-ssc"))
> -			rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
> -						 RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
> -	}
> +	if (priv->type == PHY_TYPE_PCIE && priv->enable_ssc)
> +		rockchip_combphy_updatel(priv, RK3528_PHYREG40_SSC_EN,
> +					 RK3528_PHYREG40_SSC_EN, RK3528_PHYREG40);
>  
>  	return 0;
>  }
> @@ -571,7 +569,7 @@ static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
>  	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x101 },
>  	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
>  	/* pipe-grf */
> -	.u3otg0_port_en         = { 0x0044, 15, 0, 0x0181, 0x1100 },
> +	.u3otg0_port_en		= { 0x0044, 15, 0, 0x0181, 0x1100 },
>  };
>  
>  static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
>