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Message-ID: <SJ1PR11MB6083D2E29D35B29A9C2C4317FC0EA@SJ1PR11MB6083.namprd11.prod.outlook.com>
Date: Wed, 10 Sep 2025 17:23:05 +0000
From: "Luck, Tony" <tony.luck@...el.com>
To: Nikolay Borisov <nik.borisov@...e.com>, Yazen Ghannam
	<yazen.ghannam@....com>, "x86@...nel.org" <x86@...nel.org>, "Rafael J.
 Wysocki" <rafael@...nel.org>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-edac@...r.kernel.org" <linux-edac@...r.kernel.org>,
	"Smita.KoralahalliChannabasappa@....com"
	<Smita.KoralahalliChannabasappa@....com>, "Zhuo, Qiuxu"
	<qiuxu.zhuo@...el.com>, "linux-acpi@...r.kernel.org"
	<linux-acpi@...r.kernel.org>
Subject: RE: [PATCH v6 02/15] x86/mce: Define BSP-only init

> nit: One question though for those CPUs which consist of P+E cores, is 
> it mandated that both types of cores will have identical MCE 
> architecture, I assume the x86 world will be a lot more unified than 
> Arm's big.LITTLE ?

Intel P and E cores have the same architectural MCE behavior (though the
model specific bits like IA32_MCi_MISC and IA32_STATUS.MSCOD could
be different on cores in the same hybrid part).

-Tony

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