[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1096bc24-2bac-4bc2-bc4f-9d653839e81d@amd.com>
Date: Wed, 10 Sep 2025 14:49:23 -0500
From: "Moger, Babu" <babu.moger@....com>
To: Borislav Petkov <bp@...en8.de>
Cc: corbet@....net, tony.luck@...el.com, reinette.chatre@...el.com,
Dave.Martin@....com, james.morse@....com, tglx@...utronix.de,
mingo@...hat.com, dave.hansen@...ux.intel.com, x86@...nel.org,
hpa@...or.com, kas@...nel.org, rick.p.edgecombe@...el.com,
akpm@...ux-foundation.org, paulmck@...nel.org, frederic@...nel.org,
pmladek@...e.com, rostedt@...dmis.org, kees@...nel.org, arnd@...db.de,
fvdl@...gle.com, seanjc@...gle.com, thomas.lendacky@....com,
pawan.kumar.gupta@...ux.intel.com, perry.yuan@....com,
manali.shukla@....com, sohil.mehta@...el.com, xin@...or.com,
Neeraj.Upadhyay@....com, peterz@...radead.org, tiala@...rosoft.com,
mario.limonciello@....com, dapeng1.mi@...ux.intel.com, michael.roth@....com,
chang.seok.bae@...el.com, linux-doc@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-coco@...ts.linux.dev,
kvm@...r.kernel.org, peternewman@...gle.com, eranian@...gle.com,
gautham.shenoy@....com
Subject: Re: [PATCH v18 14/33] x86/resctrl: Add data structures and
definitions for ABMC assignment
Hi Boris,
On 9/10/25 12:26, Borislav Petkov wrote:
> On Fri, Sep 05, 2025 at 04:34:13PM -0500, Babu Moger wrote:
>> diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
>> index 18222527b0ee..48230814098d 100644
>> --- a/arch/x86/include/asm/msr-index.h
>> +++ b/arch/x86/include/asm/msr-index.h
>> @@ -1232,6 +1232,7 @@
>> /* - AMD: */
>> #define MSR_IA32_MBA_BW_BASE 0xc0000200
>> #define MSR_IA32_SMBA_BW_BASE 0xc0000280
>> +#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd
>> #define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff
>> #define MSR_IA32_EVT_CFG_BASE 0xc0000400
>
> Some of those MSRs are AMD-specific: why do they have "IA32" in the name and
> not "AMD64"?
>
No particular reason — it was just carried over from older MSRs by copy-paste.
In fact, all five of them are AMD-specific in this case. Let me know the
best way to handle this.
--
Thanks
Babu Moger
Powered by blists - more mailing lists