linux-kernel - Re: [PATCH v7 1/2] dt-bindings: usb: dwc3: add support for SpacemiT K1

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Message-ID: <aMH5P3Xae0MCt6wu@lizhi-Precision-Tower-5810>
Date: Wed, 10 Sep 2025 18:18:39 -0400
From: Frank Li <Frank.li@....com>
To: Ze Huang <huang.ze@...ux.dev>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>, Yixun Lan <dlan@...too.org>,
	Thinh Nguyen <Thinh.Nguyen@...opsys.com>,
	Philipp Zabel <p.zabel@...gutronix.de>, linux-usb@...r.kernel.org,
	devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org,
	spacemit@...ts.linux.dev, linux-kernel@...r.kernel.org,
	Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: Re: [PATCH v7 1/2] dt-bindings: usb: dwc3: add support for SpacemiT
 K1

On Tue, Jul 29, 2025 at 12:33:55AM +0800, Ze Huang wrote:
> Add support for the USB 3.0 Dual-Role Device (DRD) controller embedded
> in the SpacemiT K1 SoC. The controller is based on the Synopsys
> DesignWare Core USB 3 (DWC3) IP, supporting USB3.0 host mode and USB 2.0
> DRD mode.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> Signed-off-by: Ze Huang <huang.ze@...ux.dev>
> ---

Ze Huang:

   I seen Krzysztof and Thinh Nguyen already acked this patches. Do you
wait for greg pick it up or need respin?

   My one layerscape usb patch depend on this one!

Frank

>  .../devicetree/bindings/usb/spacemit,k1-dwc3.yaml  | 124 +++++++++++++++++++++
>  1 file changed, 124 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> new file mode 100644
> index 0000000000000000000000000000000000000000..7007e2bd42016ae0e50c4007e75d26bada34d983
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/spacemit,k1-dwc3.yaml
> @@ -0,0 +1,124 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/usb/spacemit,k1-dwc3.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: SpacemiT K1 SuperSpeed DWC3 USB SoC Controller
> +
> +maintainers:
> +  - Ze Huang <huang.ze@...ux.dev>
> +
> +description: |
> +  The SpacemiT K1 embeds a DWC3 USB IP Core which supports Host functions
> +  for USB 3.0 and DRD for USB 2.0.
> +
> +  Key features:
> +  - USB3.0 SuperSpeed and USB2.0 High/Full/Low-Speed support
> +  - Supports low-power modes (USB2.0 suspend, USB3.0 U1/U2/U3)
> +  - Internal DMA controller and flexible endpoint FIFO sizing
> +
> +  Communication Interface:
> +  - Use of PIPE3 (125MHz) interface for USB3.0 PHY
> +  - Use of UTMI+ (30/60MHz) interface for USB2.0 PHY
> +
> +allOf:
> +  - $ref: snps,dwc3-common.yaml#
> +
> +properties:
> +  compatible:
> +    const: spacemit,k1-dwc3
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  clock-names:
> +    const: usbdrd30
> +
> +  interrupts:
> +    maxItems: 1
> +
> +  phys:
> +    items:
> +      - description: phandle to USB2/HS PHY
> +      - description: phandle to USB3/SS PHY
> +
> +  phy-names:
> +    items:
> +      - const: usb2-phy
> +      - const: usb3-phy
> +
> +  resets:
> +    items:
> +      - description: USB3.0 AHB reset
> +      - description: USB3.0 VCC reset
> +      - description: USB3.0 PHY reset
> +      - description: PCIE0 global reset (for combo phy)
> +
> +  reset-names:
> +    items:
> +      - const: ahb
> +      - const: vcc
> +      - const: phy
> +      - const: pcie0
> +
> +  reset-delay:
> +    $ref: /schemas/types.yaml#/definitions/uint32
> +    default: 2
> +    description: delay after reset sequence [us]
> +
> +  vbus-supply:
> +    description: A phandle to the regulator supplying the VBUS voltage.
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - interrupts
> +  - phys
> +  - phy-names
> +  - resets
> +  - reset-names
> +
> +unevaluatedProperties: false
> +
> +examples:
> +  - |
> +    usb@...00000 {
> +        compatible = "spacemit,k1-dwc3";
> +        reg = <0xc0a00000 0x10000>;
> +        clocks = <&syscon_apmu 16>;
> +        clock-names = "usbdrd30";
> +        interrupts = <125>;
> +        phys = <&usb2phy>, <&usb3phy>;
> +        phy-names = "usb2-phy", "usb3-phy";
> +        resets = <&syscon_apmu 8>,
> +                 <&syscon_apmu 9>,
> +                 <&syscon_apmu 10>,
> +                 <&syscon_apmu 26>;
> +        reset-names = "ahb", "vcc", "phy", "pcie0";
> +        reset-delay = <2>;
> +        vbus-supply = <&usb3_vbus>;
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        hub_2_0: hub@1 {
> +            compatible = "usb2109,2817";
> +            reg = <1>;
> +            vdd-supply = <&usb3_vhub>;
> +            peer-hub = <&hub_3_0>;
> +            reset-gpios = <&gpio 3 28 1>;
> +        };
> +
> +        hub_3_0: hub@2 {
> +            compatible = "usb2109,817";
> +            reg = <2>;
> +            vdd-supply = <&usb3_vhub>;
> +            peer-hub = <&hub_2_0>;
> +            reset-gpios = <&gpio 3 28 1>;
> +        };
> +    };
>
> --
> 2.50.1
>