[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Message-Id: <20250911-preemption_aware_hangcheck-v1-0-974819876819@gmail.com>
Date: Thu, 11 Sep 2025 19:01:03 +0200
From: Anna Maniscalco <anna.maniscalco2000@...il.com>
To: Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
Konrad Dybcio <konradybcio@...nel.org>, Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Anna Maniscalco <anna.maniscalco2000@...il.com>
Subject: [PATCH 0/2] Make hang check aware of preemption
Ever since we added support for preemption hangcheck has been somewhat
broken as it is not aware of multiple rings.
In some cases it might not recognize that one ring is stuck if the gpu
switches in and out of it.
Signed-off-by: Anna Maniscalco <anna.maniscalco2000@...il.com>
---
Anna Maniscalco (2):
drm/msm/registers: Sync GPU registers from mesa
drm/msm: preemption aware hangcheck
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 3 +-
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 28 +++++++++++++--
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 25 +++++++++----
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 3 +-
drivers/gpu/drm/msm/msm_gpu.c | 51 +++++++++++++++++++++------
drivers/gpu/drm/msm/msm_gpu.h | 3 ++
drivers/gpu/drm/msm/msm_ringbuffer.h | 6 ++++
drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 1 +
10 files changed, 103 insertions(+), 21 deletions(-)
---
base-commit: b5bad77e1e3c7249e4c0c88f98477e1ee7669b63
change-id: 20250911-preemption_aware_hangcheck-8b9b3708efcc
Best regards,
--
Anna Maniscalco <anna.maniscalco2000@...il.com>
Powered by blists - more mailing lists