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Message-ID: <CAMRc=MedZ3ub=7gacx_sW0C9f9Ra5XC94xgwLTt_7iq=Y4UFEA@mail.gmail.com>
Date: Thu, 11 Sep 2025 09:58:00 +0200
From: Bartosz Golaszewski <brgl@...ev.pl>
To: Samuel Holland <samuel.holland@...ive.com>
Cc: linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-mips@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org, linux-riscv@...ts.infradead.org,
spacemit@...ts.linux.dev,
Bartosz Golaszewski <bartosz.golaszewski@...aro.org>, Linus Walleij <linus.walleij@...aro.org>,
Keguang Zhang <keguang.zhang@...il.com>, Alban Bedel <albeu@...e.fr>, Doug Berger <opendmb@...il.com>,
Florian Fainelli <florian.fainelli@...adcom.com>,
Broadcom internal kernel review list <bcm-kernel-feedback-list@...adcom.com>,
Matthias Brugger <matthias.bgg@...il.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
Paul Walmsley <paul.walmsley@...ive.com>, Yixun Lan <dlan@...too.org>,
Andy Shevchenko <andy@...nel.org>
Subject: Re: [PATCH v2 11/15] gpio: sifive: use new generic GPIO chip API
On Thu, Sep 11, 2025 at 2:37 AM Samuel Holland
<samuel.holland@...ive.com> wrote:
>
> Hi Bartosz,
>
> On 2025-09-10 2:12 AM, Bartosz Golaszewski wrote:
> > From: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> >
> > Convert the driver to using the new generic GPIO chip interfaces from
> > linux/gpio/generic.h.
> >
> > Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@...aro.org>
> > ---
> > drivers/gpio/gpio-sifive.c | 73 ++++++++++++++++++++++++----------------------
> > 1 file changed, 38 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/gpio/gpio-sifive.c b/drivers/gpio/gpio-sifive.c
> > index 98ef975c44d9a6c9238605cfd1d5820fd70a66ca..2ced87ffd3bbf219c11857391eb4ea808adc0527 100644
> > --- a/drivers/gpio/gpio-sifive.c
> > +++ b/drivers/gpio/gpio-sifive.c
> > @@ -7,6 +7,7 @@
> > #include <linux/device.h>
> > #include <linux/errno.h>
> > #include <linux/gpio/driver.h>
> > +#include <linux/gpio/generic.h>
> > #include <linux/init.h>
> > #include <linux/platform_device.h>
> > #include <linux/property.h>
> > @@ -32,7 +33,7 @@
> >
> > struct sifive_gpio {
> > void __iomem *base;
> > - struct gpio_chip gc;
> > + struct gpio_generic_chip gen_gc;
> > struct regmap *regs;
> > unsigned long irq_state;
> > unsigned int trigger[SIFIVE_GPIO_MAX];
> > @@ -41,10 +42,10 @@ struct sifive_gpio {
> >
> > static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
> > {
> > - unsigned long flags;
> > unsigned int trigger;
> >
> > - raw_spin_lock_irqsave(&chip->gc.bgpio_lock, flags);
> > + guard(gpio_generic_lock_irqsave)(&chip->gen_gc);
> > +
> > trigger = (chip->irq_state & BIT(offset)) ? chip->trigger[offset] : 0;
> > regmap_update_bits(chip->regs, SIFIVE_GPIO_RISE_IE, BIT(offset),
> > (trigger & IRQ_TYPE_EDGE_RISING) ? BIT(offset) : 0);
> > @@ -54,7 +55,6 @@ static void sifive_gpio_set_ie(struct sifive_gpio *chip, unsigned int offset)
> > (trigger & IRQ_TYPE_LEVEL_HIGH) ? BIT(offset) : 0);
> > regmap_update_bits(chip->regs, SIFIVE_GPIO_LOW_IE, BIT(offset),
> > (trigger & IRQ_TYPE_LEVEL_LOW) ? BIT(offset) : 0);
> > - raw_spin_unlock_irqrestore(&chip->gc.bgpio_lock, flags);
> > }
> >
> > static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
> > @@ -72,13 +72,12 @@ static int sifive_gpio_irq_set_type(struct irq_data *d, unsigned int trigger)
> > }
> >
> > static void sifive_gpio_irq_enable(struct irq_data *d)
> > -{
> > + {
>
> This looks like an unintentional whitespace change.
>
Ah, thanks, checkpatch did not spot it. I'll fix it when applying.
> > struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
> > struct sifive_gpio *chip = gpiochip_get_data(gc);
> > irq_hw_number_t hwirq = irqd_to_hwirq(d);
> > int offset = hwirq % SIFIVE_GPIO_MAX;
> > u32 bit = BIT(offset);
> > - unsigned long flags;
> >
> > gpiochip_enable_irq(gc, hwirq);
> > irq_chip_enable_parent(d);
> > @@ -86,13 +85,13 @@ static void sifive_gpio_irq_enable(struct irq_data *d)
> > /* Switch to input */
> > gc->direction_input(gc, offset);
> >
> > - raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
> > - /* Clear any sticky pending interrupts */
> > - regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
> > - regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
> > - regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
> > - regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
> > - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
> > + scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) {
> > + /* Clear any sticky pending interrupts */
> > + regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
> > + regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
> > + regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
> > + regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
> > + }
>
> This block (and the copy below) don't actually need any locking, since these are
> R/W1C bits. From the manual: "Once the interrupt is pending, it will remain set
> until a 1 is written to the *_ip register at that bit." I can send this as a
> follow-up improvement if you want to keep this limited to the API conversion.
>
Sure, please do.
> So with the minor whitespace fix:
> Reviewed-by: Samuel Holland <samuel.holland@...ive.com>
>
Thanks,
Bart
> Regards,
> Samuel
>
> >
> > /* Enable interrupts */
> > assign_bit(offset, &chip->irq_state, 1);
> > @@ -118,15 +117,14 @@ static void sifive_gpio_irq_eoi(struct irq_data *d)
> > struct sifive_gpio *chip = gpiochip_get_data(gc);
> > int offset = irqd_to_hwirq(d) % SIFIVE_GPIO_MAX;
> > u32 bit = BIT(offset);
> > - unsigned long flags;
> >
> > - raw_spin_lock_irqsave(&gc->bgpio_lock, flags);
> > - /* Clear all pending interrupts */
> > - regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
> > - regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
> > - regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
> > - regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
> > - raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags);
> > + scoped_guard(gpio_generic_lock_irqsave, &chip->gen_gc) {
> > + /* Clear all pending interrupts */
> > + regmap_write(chip->regs, SIFIVE_GPIO_RISE_IP, bit);
> > + regmap_write(chip->regs, SIFIVE_GPIO_FALL_IP, bit);
> > + regmap_write(chip->regs, SIFIVE_GPIO_HIGH_IP, bit);
> > + regmap_write(chip->regs, SIFIVE_GPIO_LOW_IP, bit);
> > + }
> >
> > irq_chip_eoi_parent(d);
> > }
> > @@ -179,6 +177,7 @@ static const struct regmap_config sifive_gpio_regmap_config = {
> >
> > static int sifive_gpio_probe(struct platform_device *pdev)
> > {
> > + struct gpio_generic_chip_config config;
> > struct device *dev = &pdev->dev;
> > struct irq_domain *parent;
> > struct gpio_irq_chip *girq;
> > @@ -217,13 +216,17 @@ static int sifive_gpio_probe(struct platform_device *pdev)
> > */
> > parent = irq_get_irq_data(chip->irq_number[0])->domain;
> >
> > - ret = bgpio_init(&chip->gc, dev, 4,
> > - chip->base + SIFIVE_GPIO_INPUT_VAL,
> > - chip->base + SIFIVE_GPIO_OUTPUT_VAL,
> > - NULL,
> > - chip->base + SIFIVE_GPIO_OUTPUT_EN,
> > - chip->base + SIFIVE_GPIO_INPUT_EN,
> > - BGPIOF_READ_OUTPUT_REG_SET);
> > + config = (struct gpio_generic_chip_config) {
> > + .dev = dev,
> > + .sz = 4,
> > + .dat = chip->base + SIFIVE_GPIO_INPUT_VAL,
> > + .set = chip->base + SIFIVE_GPIO_OUTPUT_VAL,
> > + .dirout = chip->base + SIFIVE_GPIO_OUTPUT_EN,
> > + .dirin = chip->base + SIFIVE_GPIO_INPUT_EN,
> > + .flags = BGPIOF_READ_OUTPUT_REG_SET,
> > + };
> > +
> > + ret = gpio_generic_chip_init(&chip->gen_gc, &config);
> > if (ret) {
> > dev_err(dev, "unable to init generic GPIO\n");
> > return ret;
> > @@ -236,12 +239,12 @@ static int sifive_gpio_probe(struct platform_device *pdev)
> > regmap_write(chip->regs, SIFIVE_GPIO_LOW_IE, 0);
> > chip->irq_state = 0;
> >
> > - chip->gc.base = -1;
> > - chip->gc.ngpio = ngpio;
> > - chip->gc.label = dev_name(dev);
> > - chip->gc.parent = dev;
> > - chip->gc.owner = THIS_MODULE;
> > - girq = &chip->gc.irq;
> > + chip->gen_gc.gc.base = -1;
> > + chip->gen_gc.gc.ngpio = ngpio;
> > + chip->gen_gc.gc.label = dev_name(dev);
> > + chip->gen_gc.gc.parent = dev;
> > + chip->gen_gc.gc.owner = THIS_MODULE;
> > + girq = &chip->gen_gc.gc.irq;
> > gpio_irq_chip_set_chip(girq, &sifive_gpio_irqchip);
> > girq->fwnode = dev_fwnode(dev);
> > girq->parent_domain = parent;
> > @@ -249,7 +252,7 @@ static int sifive_gpio_probe(struct platform_device *pdev)
> > girq->handler = handle_bad_irq;
> > girq->default_type = IRQ_TYPE_NONE;
> >
> > - return gpiochip_add_data(&chip->gc, chip);
> > + return gpiochip_add_data(&chip->gen_gc.gc, chip);
> > }
> >
> > static const struct of_device_id sifive_gpio_match[] = {
> >
>
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