linux-kernel - Re: [PATCH v2 3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver

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Message-ID:
 <MAUPR01MB1107224119A8D402FEBE5E2D0FE09A@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM>
Date: Thu, 11 Sep 2025 08:09:24 +0800
From: Chen Wang <unicorn_wang@...look.com>
To: Bjorn Helgaas <helgaas@...nel.org>, Chen Wang <unicornxw@...il.com>
Cc: kwilczynski@...nel.org, u.kleine-koenig@...libre.com,
 aou@...s.berkeley.edu, alex@...ti.fr, arnd@...db.de, bwawrzyn@...co.com,
 bhelgaas@...gle.com, conor+dt@...nel.org, 18255117159@....com,
 inochiama@...il.com, kishon@...nel.org, krzk+dt@...nel.org,
 lpieralisi@...nel.org, mani@...nel.org, palmer@...belt.com,
 paul.walmsley@...ive.com, robh@...nel.org, s-vadapalli@...com,
 tglx@...utronix.de, thomas.richard@...tlin.com, sycamoremoon376@...il.com,
 devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
 linux-pci@...r.kernel.org, linux-riscv@...ts.infradead.org,
 sophgo@...ts.linux.dev, rabenda.cn@...il.com, chao.wei@...hgo.com,
 xiaoguang.xing@...hgo.com, fengchun.li@...hgo.com
Subject: Re: [PATCH v2 3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver


On 9/10/2025 10:34 PM, Bjorn Helgaas wrote:
> On Wed, Sep 10, 2025 at 10:08:39AM +0800, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@...look.com>
>>
>> Add support for PCIe controller in SG2042 SoC. The controller
>> uses the Cadence PCIe core programmed by pcie-cadence*.c. The
>> PCIe controller will work in host mode only, supporting data
>> rate(gen4) and lanes(x16 or x8).
> Strictly speaking, "gen4" is a spec revision, not a data rate.
> Include the GT/s rate instead or in addition.  We can fix this when
> merging if there's no other reason to repost (I assume you mean 16
> GT/s).  Will also add spaces before the open "(".

Yes, I meant 16 GT/s.

Please help fix this when merging together with dropping period at end 
of subject for the [2/7], if no repost.

Thanks,

Chen