linux-kernel - Re: [PATCH v2 3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver

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Message-ID: <20250910143453.GA1533730@bhelgaas>
Date: Wed, 10 Sep 2025 09:34:53 -0500
From: Bjorn Helgaas <helgaas@...nel.org>
To: Chen Wang <unicornxw@...il.com>
Cc: kwilczynski@...nel.org, u.kleine-koenig@...libre.com,
	aou@...s.berkeley.edu, alex@...ti.fr, arnd@...db.de,
	bwawrzyn@...co.com, bhelgaas@...gle.com, unicorn_wang@...look.com,
	conor+dt@...nel.org, 18255117159@....com, inochiama@...il.com,
	kishon@...nel.org, krzk+dt@...nel.org, lpieralisi@...nel.org,
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	robh@...nel.org, s-vadapalli@...com, tglx@...utronix.de,
	thomas.richard@...tlin.com, sycamoremoon376@...il.com,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org, linux-riscv@...ts.infradead.org,
	sophgo@...ts.linux.dev, rabenda.cn@...il.com, chao.wei@...hgo.com,
	xiaoguang.xing@...hgo.com, fengchun.li@...hgo.com
Subject: Re: [PATCH v2 3/7] PCI: sg2042: Add Sophgo SG2042 PCIe driver

On Wed, Sep 10, 2025 at 10:08:39AM +0800, Chen Wang wrote:
> From: Chen Wang <unicorn_wang@...look.com>
> 
> Add support for PCIe controller in SG2042 SoC. The controller
> uses the Cadence PCIe core programmed by pcie-cadence*.c. The
> PCIe controller will work in host mode only, supporting data
> rate(gen4) and lanes(x16 or x8).

Strictly speaking, "gen4" is a spec revision, not a data rate.
Include the GT/s rate instead or in addition.  We can fix this when
merging if there's no other reason to repost (I assume you mean 16
GT/s).  Will also add spaces before the open "(".