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Message-ID: <20250912141436.2347852-1-vincent.guittot@linaro.org>
Date: Fri, 12 Sep 2025 16:14:32 +0200
From: Vincent Guittot <vincent.guittot@...aro.org>
To: chester62515@...il.com,
mbrugger@...e.com,
ghennadi.procopciuc@....nxp.com,
s32@....com,
lpieralisi@...nel.org,
kwilczynski@...nel.org,
mani@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
Ionut.Vicovan@....com,
larisa.grigore@....com,
Ghennadi.Procopciuc@....com,
ciprianmarian.costea@....com,
bogdan.hamciuc@....com,
linux-arm-kernel@...ts.infradead.org,
linux-pci@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 0/4] pcie: s32g: Add support for PCIe controller
The S32G SoC family has 2 PCIe controllers based on Designware IP.
Add the support for Host mode.
Ciprian Costea (1):
pcie: s32g: Add Phy clock definition
Vincent Guittot (3):
dt-bindings: pcie: Add the NXP PCIe controller
pcie: s32g: Add initial PCIe support (RC)
MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver
.../devicetree/bindings/pci/nxp,s32-pcie.yaml | 169 +++++
MAINTAINERS | 3 +
drivers/pci/controller/dwc/Kconfig | 12 +
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pci-s32g-regs.h | 105 +++
drivers/pci/controller/dwc/pci-s32g.c | 697 ++++++++++++++++++
drivers/pci/controller/dwc/pci-s32g.h | 45 ++
.../linux/pcie/nxp-s32g-pcie-phy-submode.h | 15 +
8 files changed, 1047 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/nxp,s32-pcie.yaml
create mode 100644 drivers/pci/controller/dwc/pci-s32g-regs.h
create mode 100644 drivers/pci/controller/dwc/pci-s32g.c
create mode 100644 drivers/pci/controller/dwc/pci-s32g.h
create mode 100644 include/linux/pcie/nxp-s32g-pcie-phy-submode.h
--
2.43.0
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