linux-kernel - Re: [PATCH v3 1/4] KVM: x86: relax canonical check for some x86 architectural msrs

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Message-ID: <CALMp9eR91k0t9kSzpvM=-=yePGYmLHggjfvvhmD-qaxBCnRn+Q@mail.gmail.com>
Date: Fri, 12 Sep 2025 13:28:26 -0700
From: Jim Mattson <jmattson@...gle.com>
To: Sean Christopherson <seanjc@...gle.com>
Cc: mlevitsk@...hat.com, kvm@...r.kernel.org, Ingo Molnar <mingo@...hat.com>, 
	x86@...nel.org, Paolo Bonzini <pbonzini@...hat.com>, Thomas Gleixner <tglx@...utronix.de>, 
	Dave Hansen <dave.hansen@...ux.intel.com>, Borislav Petkov <bp@...en8.de>, linux-kernel@...r.kernel.org, 
	"H. Peter Anvin" <hpa@...or.com>, Chao Gao <chao.gao@...el.com>
Subject: Re: [PATCH v3 1/4] KVM: x86: relax canonical check for some x86
 architectural msrs

On Fri, Aug 23, 2024 at 6:59 AM Sean Christopherson <seanjc@...gle.com> wrote:
> Heh, and for MPX, the SDM kinda sorta confirms that LA57 is ignored, though I
> doubt the author of this section intended their words to be taken this way :-)
>
>   WRMSR to BNDCFGS will #GP if any of the reserved bits of BNDCFGS is not zero or
>   if the base address of the bound directory is not canonical. XRSTOR of BNDCFGU
>   ignores the reserved bits and does not fault if any is non-zero; similarly, it
>   ignores the upper bits of the base address of the bound directory and sign-extends
>   the highest implemented bit of the linear address to guarantee the canonicality
>   ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>   of this address.

I don't believe there was ever a CPU that supported both MPX and LA57. :)

Late to the party, as usual, but my interest was piqued by the failure
of KVM_SET_NESTED_STATE prior to v6.13 if L1 had CR4.LA57 set, L2 did
not, and the VMCS12.HOST_GSBASE had a kernel address > 48 bits wide.
The canonicalization checks for the *host* state in the VMCS were done
using the guest's CR4.LA57.

Shouldn't this series have been cc'd to stable?