lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID:
 <DS3PR21MB5878ED61E035A30E36E62CFABF08A@DS3PR21MB5878.namprd21.prod.outlook.com>
Date: Fri, 12 Sep 2025 20:45:11 +0000
From: Dexuan Cui <decui@...rosoft.com>
To: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>, "x86@...nel.org"
	<x86@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
	<conor+dt@...nel.org>, Rob Herring <robh@...nel.org>, KY Srinivasan
	<kys@...rosoft.com>, Haiyang Zhang <haiyangz@...rosoft.com>, Wei Liu
	<wei.liu@...nel.org>, Michael Kelley <mhklinux@...look.com>, "Rafael J.
 Wysocki" <rafael@...nel.org>
CC: "ssengar@...ux.microsoft.com" <ssengar@...ux.microsoft.com>, Chris Oo
	<cho@...rosoft.com>, "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
	"linux-hyperv@...r.kernel.org" <linux-hyperv@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Ricardo Neri
	<ricardo.neri@...el.com>, Yunhong Jiang <yunhong.jiang@...ux.intel.com>,
	Thomas Gleixner <tglx@...utronix.de>
Subject: RE: [EXTERNAL] [PATCH v5 06/10] x86/realmode: Make the location of
 the trampoline configurable

> From: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> Sent: Friday, June 27, 2025 8:35 PM
> [...]
> From: Yunhong Jiang <yunhong.jiang@...ux.intel.com>
> 
> x86 CPUs boot in real mode. This mode uses 20-bit memory addresses (16-bit
> registers plus 4-bit segment selectors). This implies that the trampoline
> must reside under the 1MB memory boundary.
> 
> There are platforms in which the firmware boots the secondary CPUs,
> switches them to long mode and transfers control to the kernel. An example
> of such mechanism is the ACPI Multiprocessor Wakeup Structure.
> 
> In this scenario there is no restriction to locate the trampoline under 1MB
> memory. Moreover, certain platforms (for example, Hyper-V VTL guests) may
> not have memory available for allocation under 1MB.
> 
> Add a new member to struct x86_init_resources to specify the upper bound
> for the location of the trampoline memory. Keep the default upper bound of
> 1MB to conserve the current behavior.
> 
> Reviewed-by: Michael Kelley <mhklinux@...look.com>
> Originally-by: Thomas Gleixner <tglx@...utronix.de>
> Signed-off-by: Yunhong Jiang <yunhong.jiang@...ux.intel.com>
> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> ---

LGTM

Reviewed-by: Dexuan Cui <decui@...rosoft.com>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ