linux-kernel - RE: [EXTERNAL] [PATCH v5 07/10] x86/hyperv/vtl: Setup the 64-bit trampoline for TDX guests

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Message-ID:
 <DS3PR21MB5878147F5FE71FF6243BA160BF08A@DS3PR21MB5878.namprd21.prod.outlook.com>
Date: Fri, 12 Sep 2025 20:45:40 +0000
From: Dexuan Cui <decui@...rosoft.com>
To: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>, "x86@...nel.org"
	<x86@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
	<conor+dt@...nel.org>, Rob Herring <robh@...nel.org>, KY Srinivasan
	<kys@...rosoft.com>, Haiyang Zhang <haiyangz@...rosoft.com>, Wei Liu
	<wei.liu@...nel.org>, Michael Kelley <mhklinux@...look.com>, "Rafael J.
 Wysocki" <rafael@...nel.org>
CC: "ssengar@...ux.microsoft.com" <ssengar@...ux.microsoft.com>, Chris Oo
	<cho@...rosoft.com>, "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
	"linux-hyperv@...r.kernel.org" <linux-hyperv@...r.kernel.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-acpi@...r.kernel.org" <linux-acpi@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, Ricardo Neri
	<ricardo.neri@...el.com>, Yunhong Jiang <yunhong.jiang@...ux.intel.com>
Subject: RE: [EXTERNAL] [PATCH v5 07/10] x86/hyperv/vtl: Setup the 64-bit
 trampoline for TDX guests

> From: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> Sent: Friday, June 27, 2025 8:35 PM
> [...]
> From: Yunhong Jiang <yunhong.jiang@...ux.intel.com>
> 
> The hypervisor is an untrusted entity for TDX guests. It cannot be used
> to boot secondary CPUs - neither via hypercalls not the INIT assert,
> de-assert plus Start-Up IPI messages.
> 
> Instead, the platform virtual firmware boots the secondary CPUs and
> puts them in a state to transfer control to the kernel. This mechanism uses
> the wakeup mailbox described in the Multiprocessor Wakeup Structure of the
> ACPI specification. The entry point to the kernel is trampoline_start64.
> 
> Allocate and setup the trampoline using the default x86_platform callbacks.
> 
> The platform firmware configures the secondary CPUs in long mode. It is no
> longer necessary to locate the trampoline under 1MB memory. After handoff
> from firmware, the trampoline code switches briefly to 32-bit addressing
> mode, which has an addressing limit of 4GB. Set the upper bound of the
> trampoline memory accordingly.
> 
> Reviewed-by: Michael Kelley <mhklinux@...look.com>
> Signed-off-by: Yunhong Jiang <yunhong.jiang@...ux.intel.com>
> Signed-off-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>
> ---

LGTM

Reviewed-by: Dexuan Cui <decui@...rosoft.com>