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Message-ID: <20250916100417.3036847-4-randolph@andestech.com>
Date: Tue, 16 Sep 2025 18:04:15 +0800
From: Randolph Lin <randolph@...estech.com>
To: <linux-kernel@...r.kernel.org>
CC: <linux-pci@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <jingoohan1@...il.com>,
<mani@...nel.org>, <lpieralisi@...nel.org>, <kwilczynski@...nel.org>,
<robh@...nel.org>, <bhelgaas@...gle.com>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <alex@...ti.fr>, <aou@...s.berkeley.edu>,
<palmer@...belt.com>, <paul.walmsley@...ive.com>,
<ben717@...estech.com>, <inochiama@...il.com>,
<thippeswamy.havalige@....com>, <namcao@...utronix.de>,
<shradha.t@...sung.com>, <randolph.sklin@...il.com>,
<tim609@...estech.com>, Randolph Lin <randolph@...estech.com>
Subject: [PATCH v2 3/5] riscv: dts: andes: Add PCIe node into the QiLai SoC
Add the Andes QiLai PCIe node, which includes 3 Root Complexes.
Signed-off-by: Randolph Lin <randolph@...estech.com>
---
arch/riscv/boot/dts/andes/qilai.dtsi | 109 +++++++++++++++++++++++++++
1 file changed, 109 insertions(+)
diff --git a/arch/riscv/boot/dts/andes/qilai.dtsi b/arch/riscv/boot/dts/andes/qilai.dtsi
index de3de32f8c39..d475b5fe2356 100644
--- a/arch/riscv/boot/dts/andes/qilai.dtsi
+++ b/arch/riscv/boot/dts/andes/qilai.dtsi
@@ -182,5 +182,114 @@ uart0: serial@...00000 {
reg-io-width = <4>;
no-loopback-test;
};
+
+ bus@...00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0x80000000 0x00 0x80000000 0x00 0x20000000>,
+ <0x00 0x04000000 0x00 0x04000000 0x00 0x00001000>,
+ <0x00 0x00000000 0x20 0x00000000 0x20 0x00000000>;
+
+ pci@...00000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0x80000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04000000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ bus-range = <0x0 0xff>;
+ num-viewport = <4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x00 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x1f 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xf 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xf 0x4>,
+ <0 0 0 2 &plic 0xf 0x4>,
+ <0 0 0 3 &plic 0xf 0x4>,
+ <0 0 0 4 &plic 0xf 0x4>;
+ };
+ };
+
+ bus@...00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xa0000000 0x00 0xa0000000 0x00 0x20000000>,
+ <0x00 0x04001000 0x00 0x04001000 0x00 0x00001000>,
+ <0x00 0x00000000 0x10 0x00000000 0x08 0x00000000>;
+
+ pci@...00000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xa0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04001000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ bus-range = <0x0 0xff>;
+ num-viewport = <4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xe 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xe 0x4>,
+ <0 0 0 2 &plic 0xe 0x4>,
+ <0 0 0 3 &plic 0xe 0x4>,
+ <0 0 0 4 &plic 0xe 0x4>;
+ };
+ };
+
+ bus@...00000 {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ dma-ranges = <0x44 0x00000000 0x04 0x00000000 0x04 0x00000000>;
+ ranges = <0x00 0xc0000000 0x00 0xc0000000 0x00 0x20000000>,
+ <0x00 0x04002000 0x00 0x04002000 0x00 0x00001000>,
+ <0x00 0x00000000 0x18 0x00000000 0x08 0x00000000>;
+
+ pci@...00000 {
+ compatible = "andestech,qilai-pcie";
+ device_type = "pci";
+ reg = <0x00 0xc0000000 0x00 0x20000000>, /* DBI registers */
+ <0x00 0x04002000 0x00 0x00001000>, /* APB registers */
+ <0x00 0x00000000 0x00 0x00010000>; /* Configuration registers */
+ reg-names = "dbi", "apb", "config";
+
+ bus-range = <0x0 0xff>;
+ num-viewport = <4>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x02000000 0x00 0x10000000 0x00 0x10000000 0x0 0xf0000000>,
+ <0x43000000 0x01 0x00000000 0x01 0x00000000 0x7 0x00000000>;
+
+ #interrupt-cells = <1>;
+ interrupts = <0xd 0x4>;
+ interrupt-names = "msi";
+ interrupt-parent = <&plic>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 1 &plic 0xd 0x4>,
+ <0 0 0 2 &plic 0xd 0x4>,
+ <0 0 0 3 &plic 0xd 0x4>,
+ <0 0 0 4 &plic 0xd 0x4>;
+ };
+ };
+
};
};
--
2.34.1
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