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Message-ID: <20250916100417.3036847-1-randolph@andestech.com>
Date: Tue, 16 Sep 2025 18:04:12 +0800
From: Randolph Lin <randolph@...estech.com>
To: <linux-kernel@...r.kernel.org>
CC: <linux-pci@...r.kernel.org>, <linux-riscv@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <jingoohan1@...il.com>,
<mani@...nel.org>, <lpieralisi@...nel.org>, <kwilczynski@...nel.org>,
<robh@...nel.org>, <bhelgaas@...gle.com>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>, <alex@...ti.fr>, <aou@...s.berkeley.edu>,
<palmer@...belt.com>, <paul.walmsley@...ive.com>,
<ben717@...estech.com>, <inochiama@...il.com>,
<thippeswamy.havalige@....com>, <namcao@...utronix.de>,
<shradha.t@...sung.com>, <randolph.sklin@...il.com>,
<tim609@...estech.com>, Randolph Lin <randolph@...estech.com>
Subject: [PATCH v2 0/5] Add support for Andes Qilai SoC PCIe controller
Add support for Andes Qilai SoC PCIe controller
These patches introduce driver support for the PCIe controller on the
Andes Qilai SoC.
Signed-off-by: Randolph Lin <randolph@...estech.com>
---
Changes in v2:
- Remove the patch that adds the dma-ranges property to the SoC node.
- Add dma-ranges to the PCIe parent node bus node.
- Refactor and rename outbound ATU address range validation callback and logic.
- Use parent_bus_offset instead of cpu_addr_fixup().
- Using PROBE_DEFAULT_STRATEGY as default probe type.
- Made minor adjustments based on the reviewer's suggestions.
Randolph Lin (5):
PCI: dwc: Add outbound ATU address range validation callback
dt-bindings: Add Andes QiLai PCIe support
riscv: dts: andes: Add PCIe node into the QiLai SoC
PCI: andes: Add Andes QiLai SoC PCIe host driver support
MAINTAINERS: Add maintainers for Andes QiLai PCIe driver
.../bindings/pci/andestech,qilai-pcie.yaml | 102 +++++++++
MAINTAINERS | 7 +
arch/riscv/boot/dts/andes/qilai.dtsi | 109 +++++++++
drivers/pci/controller/dwc/Kconfig | 16 ++
drivers/pci/controller/dwc/Makefile | 1 +
drivers/pci/controller/dwc/pcie-andes-qilai.c | 214 ++++++++++++++++++
drivers/pci/controller/dwc/pcie-designware.c | 29 ++-
drivers/pci/controller/dwc/pcie-designware.h | 3 +
8 files changed, 475 insertions(+), 6 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/andestech,qilai-pcie.yaml
create mode 100644 drivers/pci/controller/dwc/pcie-andes-qilai.c
--
2.34.1
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