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Message-Id: <20250916-sfg-spidts-v2-4-b5d9024fe1c8@gmail.com>
Date: Tue, 16 Sep 2025 21:22:53 +0800
From: Zixian Zeng <sycamoremoon376@...il.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Chen Wang <unicorn_wang@...look.com>,
Inochi Amaoto <inochiama@...il.com>,
Paul Walmsley <paul.walmsley@...ive.com>,
Palmer Dabbelt <palmer@...belt.com>, Albert Ou <aou@...s.berkeley.edu>,
Alexandre Ghiti <alex@...ti.fr>
Cc: devicetree@...r.kernel.org, sophgo@...ts.linux.dev,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
Han Gao <rabenda.cn@...il.com>, Longbin Li <looong.bin@...il.com>,
Zixian Zeng <sycamoremoon376@...il.com>
Subject: [PATCH v2 4/4] riscv: dts: sophgo: Enable SPI NOR node for
SG2042_EVB_V2
Enable SPI NOR node for SG2042_EVB_V2 device tree
According to SG2042_EVB_V2 schematic, SPI-NOR Flash cannot support QSPI
due to hardware design. Thus spi-(tx|rx)-bus-width must be set to 1.
Signed-off-by: Han Gao <rabenda.cn@...il.com>
Signed-off-by: Zixian Zeng <sycamoremoon376@...il.com>
---
arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
index 46980e41b886ce17dacce791fa5f2cef14cfa214..78460b2851a231a3e06b28f9ac6bffd4700e7dab 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
+++ b/arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts
@@ -226,6 +226,18 @@ &sd {
status = "okay";
};
+&spifmc1 {
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ };
+};
+
&uart0 {
pinctrl-0 = <&uart0_cfg>;
pinctrl-names = "default";
--
2.51.0
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