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Message-ID: <23013855.EfDdHjke4D@senjougahara>
Date: Wed, 17 Sep 2025 12:14:44 +0900
From: Mikko Perttunen <mperttunen@...dia.com>
To: Thierry Reding <thierry.reding@...il.com>,
Lorenzo Pieralisi <lpieralisi@...nel.org>,
Krzysztof Wilczyński <kwilczynski@...nel.org>,
Manivannan Sadhasivam <mani@...nel.org>, Rob Herring <robh@...nel.org>,
Bjorn Helgaas <bhelgaas@...gle.com>, Jonathan Hunter <jonathanh@...dia.com>,
"open list:PCI DRIVER FOR NVIDIA TEGRA" <linux-tegra@...r.kernel.org>,
"open list:PCI DRIVER FOR NVIDIA TEGRA" <linux-pci@...r.kernel.org>,
open list <linux-kernel@...r.kernel.org>, Anand Moon <linux.amoon@...il.com>
Cc: Anand Moon <linux.amoon@...il.com>
Subject:
Re: [RFC v1 2/2] PCI: tegra: Use readl_poll_timeout() for link status polling
On Monday, September 1, 2025 4:00 AM Anand Moon wrote:
> Replace the manual `do-while` polling loops with the readl_poll_timeout()
> helper when checking the link DL_UP and DL_LINK_ACTIVE status bits
> during link bring-up. This simplifies the code by removing the open-coded
> timeout logic in favor of the standard, more robust iopoll framework.
> The change improves readability and reduces code duplication.
>
> Cc: Thierry Reding <thierry.reding@...il.com>
> Signed-off-by: Anand Moon <linux.amoon@...il.com>
> ---
> drivers/pci/controller/pci-tegra.c | 38 ++++++++++++------------------
> 1 file changed, 15 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c
> index 3841489198b64..8e850f7c84e40 100644
> --- a/drivers/pci/controller/pci-tegra.c
> +++ b/drivers/pci/controller/pci-tegra.c
> @@ -24,6 +24,7 @@
> #include <linux/irqchip/chained_irq.h>
> #include <linux/irqchip/irq-msi-lib.h>
> #include <linux/irqdomain.h>
> +#include <linux/iopoll.h>
There is already an iopoll.h include in this file, so this adds a duplicate.
> #include <linux/kernel.h>
> #include <linux/init.h>
> #include <linux/module.h>
> @@ -2157,37 +2158,28 @@ static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
> value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
> writel(value, port->base + RP_PRIV_MISC);
>
> - do {
> - unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
> -
> - do {
> - value = readl(port->base + RP_VEND_XP);
> -
> - if (value & RP_VEND_XP_DL_UP)
> - break;
> -
> - usleep_range(1000, 2000);
> - } while (--timeout);
> + while (retries--) {
> + int err;
>
> - if (!timeout) {
> + err = readl_poll_timeout(port->base + RP_VEND_XP, value,
> + value & RP_VEND_XP_DL_UP,
> + 1000,
> + TEGRA_PCIE_LINKUP_TIMEOUT * 1000);
The logic change here looks OK to me. This makes the timeout 200ms (TEGRA_PCIE_LINKUP_TIMEOUT is 200). Previously, the code looped 200 times with a 1 to 2ms sleep on each iteration. So the timeout could have been longer than 200ms previously, but not in a way that could be relied on.
> + if (err) {
> dev_dbg(dev, "link %u down, retrying\n", port->index);
> goto retry;
> }
>
> - timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
> -
> - do {
> - value = readl(port->base + RP_LINK_CONTROL_STATUS);
> -
> - if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
> - return true;
> -
> - usleep_range(1000, 2000);
> - } while (--timeout);
> + err = readl_poll_timeout(port->base + RP_LINK_CONTROL_STATUS,
> + value,
> + value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE,
> + 1000, TEGRA_PCIE_LINKUP_TIMEOUT * 1000);
> + if (!err)
> + return true;
>
> retry:
> tegra_pcie_port_reset(port);
> - } while (--retries);
> + }
>
> return false;
> }
>
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