linux-kernel - RE: [PATCH v8 2/6] clk: renesas: rzv2h-cpg: Add support for DSI clocks

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Message-ID:
 <TY3PR01MB113469BFFE54EA48AA8ECCA088617A@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Wed, 17 Sep 2025 16:28:08 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: Tomi Valkeinen <tomi.valkeinen+renesas@...asonboard.com>, "Lad, Prabhakar"
	<prabhakar.csengg@...il.com>, Chris Brandt <Chris.Brandt@...esas.com>
CC: "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
	"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>, Fabrizio Castro
	<fabrizio.castro.jz@...esas.com>, Tommaso Merciai
	<tommaso.merciai.xr@...renesas.com>, Prabhakar Mahadev Lad
	<prabhakar.mahadev-lad.rj@...renesas.com>, Andrzej Hajda
	<andrzej.hajda@...el.com>, Neil Armstrong <neil.armstrong@...aro.org>, Robert
 Foss <rfoss@...nel.org>, laurent.pinchart
	<laurent.pinchart@...asonboard.com>, Jonas Karlman <jonas@...boo.se>, Jernej
 Skrabec <jernej.skrabec@...il.com>, Maarten Lankhorst
	<maarten.lankhorst@...ux.intel.com>, Maxime Ripard <mripard@...nel.org>,
	Thomas Zimmermann <tzimmermann@...e.de>, David Airlie <airlied@...il.com>,
	Simona Vetter <simona@...ll.ch>, Rob Herring <robh@...nel.org>, Krzysztof
 Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Geert
 Uytterhoeven <geert+renesas@...der.be>, Michael Turquette
	<mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, magnus.damm
	<magnus.damm@...il.com>
Subject: RE: [PATCH v8 2/6] clk: renesas: rzv2h-cpg: Add support for DSI
 clocks

Hi Tomi,

> -----Original Message-----
> From: Tomi Valkeinen <tomi.valkeinen+renesas@...asonboard.com>
> Sent: 11 September 2025 15:26
> Subject: Re: [PATCH v8 2/6] clk: renesas: rzv2h-cpg: Add support for DSI clocks
> 
> Hi,
> 
> On 11/09/2025 11:14, Lad, Prabhakar wrote:
> > Hi Tomi,
> >
> > On Wed, Sep 10, 2025 at 1:30 PM Tomi Valkeinen
> > <tomi.valkeinen+renesas@...asonboard.com> wrote:
> >>
> >> Hi,
> >>
> >> On 03/09/2025 19:17, Prabhakar wrote:
> >>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> >>>
> >>> Add support for PLLDSI and PLLDSI divider clocks.
> >>>
> >>> Introduce the `renesas-rzv2h-cpg-pll.h` header to centralize and
> >>> share PLLDSI related data structures, limits, and algorithms between
> >>> the
> >>> RZ/V2H(P) CPG and DSI drivers.
> >>>
> >>> The DSI PLL is functionally similar to the CPG's PLLDSI, but has
> >>> slightly different parameter limits and omits the programmable
> >>> divider present in CPG. To ensure precise frequency calculations,
> >>> especially for milliHz-level accuracy needed by the DSI driver, the
> >>> shared algorithm allows both drivers to compute PLL parameters
> >>> consistently using the same logic and input clock.
> >>
> >> Can you elaborate a bit more why a new clock APIs are needed for the
> >> DSI PLL? This is the first time I have heard a DSI TX (well, any IP)
> >> require more precision than Hz. Is that really the case? Are there other reasons?
> >>
> > Im pasting the same reply from Fab
> > (https://lore.kernel.org/all/TYCPR01MB12093A7D99392BC3D6B5E5864C2BC2@T
> > YCPR01MB12093.jpnprd01.prod.outlook.com/#t)
> > for the similar concern.
> >
> > The PLL found inside the DSI IP is very similar to the PLLDSI found in
> > the CPG IP block, although the limits for some of the parameters are
> 
> Thanks. As discussed on chat, this confused me: There's a PLLDSI on CPG, which doesn't provide a DSI
> clock, but a pixel clock. And then there's a PLL in the DSI D-PHY which provides the DSI clock.
> 
> A few comments overall some for this driver but also the dsi driver:
> 
> This hardcodes the refclk rate to 24 MHz with RZ_V2H_OSC_CLK_IN_MEGA in the header file. That doesn't
> feel right, shouldn't the refclk rate come from the clock framework with clk_get_rate()?
> 
> While not v2h related, I think it would be good to have a comment in the dsi driver about how the g2l
> hs clock rate is derived directly from the pixel clock.

Now the patch [1] has this info

[1]
https://lore.kernel.org/all/20250912142056.2123725-3-chris.brandt@renesas.com/

Cheers,
Biju