linux-kernel - Re: [PATCH 2/3] dmaengine: xilinx_dma: Enable transfer chaining by removing idle restriction

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Message-Id: <DCVR2N9GKNCH.2GLNGXYTGLHOX@folker-schwesinger.de>
Date: Thu, 18 Sep 2025 07:33:07 +0000
From: "Folker Schwesinger" <dev@...ker-schwesinger.de>
To: "Suraj Gupta" <suraj.gupta2@....com>, <vkoul@...nel.org>,
 <radhey.shyam.pandey@....com>, <michal.simek@....com>
Cc: <dmaengine@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
 <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/3] dmaengine: xilinx_dma: Enable transfer chaining by
 removing idle restriction

On Wed Sep 17, 2025 at 3:36 PM CEST, Suraj Gupta wrote:
> Remove the restrictive idle check in xilinx_dma_start_transfer() that
> prevented new transfers from being queued when the channel was busy.
> Additionally, only update the CURDESC register when the active list
> is empty to avoid interfering with transfers already in progress.
> When the active list contains transfers, the hardware tail pointer
> extension mechanism handles chaining automatically.
>
> Signed-off-by: Suraj Gupta <suraj.gupta2@....com>

Tested-by: Folker Schwesinger <dev@...ker-schwesinger.de>

> ---
>  drivers/dma/xilinx/xilinx_dma.c | 5 +----
>  1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
> index 9f416eae33d0..7211c394cdca 100644
> --- a/drivers/dma/xilinx/xilinx_dma.c
> +++ b/drivers/dma/xilinx/xilinx_dma.c
> @@ -1548,9 +1548,6 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
>  	if (list_empty(&chan->pending_list))
>  		return;
>  
> -	if (!chan->idle)
> -		return;
> -
>  	head_desc = list_first_entry(&chan->pending_list,
>  				     struct xilinx_dma_tx_descriptor, node);
>  	tail_desc = list_last_entry(&chan->pending_list,
> @@ -1567,7 +1564,7 @@ static void xilinx_dma_start_transfer(struct xilinx_dma_chan *chan)
>  		dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg);
>  	}
>  
> -	if (chan->has_sg)
> +	if (chan->has_sg && list_empty(&chan->active_list))
>  		xilinx_write(chan, XILINX_DMA_REG_CURDESC,
>  			     head_desc->async_tx.phys);
>  	reg  &= ~XILINX_DMA_CR_DELAY_MAX;