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Message-Id: <20250919142325.1090059-1-pankaj.patil@oss.qualcomm.com>
Date: Fri, 19 Sep 2025 19:53:25 +0530
From: Pankaj Patil <pankaj.patil@....qualcomm.com>
To: bhelgaas@...gle.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
mani@...nel.org, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, andersson@...nel.org
Cc: linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks minItems for the fifth Glymur PCIe Controller
From: Qiang Yu <qiang.yu@....qualcomm.com>
On the Qualcomm Glymur platform, the fifth PCIe host is compatible with
the DWC controller present on the X1E80100 platform, but does not have
cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six.
Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
---
Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
index 257068a18264..61581ffbfb24 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml
@@ -32,10 +32,11 @@ properties:
- const: mhi # MHI registers
clocks:
- minItems: 7
+ minItems: 6
maxItems: 7
clock-names:
+ minItems: 6
items:
- const: aux # Auxiliary clock
- const: cfg # Configuration clock
--
2.34.1
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