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Message-ID: <175857096123.1104979.8944000757958543283.robh@kernel.org>
Date: Mon, 22 Sep 2025 14:56:01 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Pankaj Patil <pankaj.patil@....qualcomm.com>
Cc: lpieralisi@...nel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org, kwilczynski@...nel.org,
bhelgaas@...gle.com, conor+dt@...nel.org, andersson@...nel.org,
linux-arm-msm@...r.kernel.org, linux-pci@...r.kernel.org,
mani@...nel.org, krzk+dt@...nel.org
Subject: Re: [PATCH] dt-bindings: PCI: qcom,pcie-x1e80100: Set clocks
minItems for the fifth Glymur PCIe Controller
On Fri, 19 Sep 2025 19:53:25 +0530, Pankaj Patil wrote:
> From: Qiang Yu <qiang.yu@....qualcomm.com>
>
> On the Qualcomm Glymur platform, the fifth PCIe host is compatible with
> the DWC controller present on the X1E80100 platform, but does not have
> cnoc_sf_axi clock. Hence, set minItems of clocks and clock-names to six.
>
> Signed-off-by: Qiang Yu <qiang.yu@....qualcomm.com>
> Signed-off-by: Pankaj Patil <pankaj.patil@....qualcomm.com>
> ---
> Documentation/devicetree/bindings/pci/qcom,pcie-x1e80100.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Acked-by: Rob Herring (Arm) <robh@...nel.org>
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